[Qemu-devel] [PATCH 0/2] m68k: Update MCF interrupt controller and MAINTAINERS

[Qemu-devel] [PATCH 0/2] m68k: Update MCF interrupt controller and MAINTAINERS

[Thomas Huth]

Here's a patch to QOMify the ColdFire interrupt controller, and
another patch to update MAINTAINERS - I'd like to volunteer to
maintain the two orphan ColdFire machines.

Thomas Huth (2):
  hw/m68k: QOMify the ColdFire interrupt controller
  MAINTAINERS: Add odd fixer the ColdFire boards

 MAINTAINERS        |  7 +++++--
 hw/m68k/mcf_intc.c | 48 ++++++++++++++++++++++++++++++++++++++++++++----
 2 files changed, 49 insertions(+), 6 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH 1/2] hw/m68k: QOMify the ColdFire interrupt controller

[Thomas Huth]

Use type_init() and friends to adapt the ColdFire interrupt
controller to the latest QEMU device conventions.

Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
 hw/m68k/mcf_intc.c | 48 ++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 44 insertions(+), 4 deletions(-)

diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c
index cf58132..8198afa 100644
--- a/hw/m68k/mcf_intc.c
+++ b/hw/m68k/mcf_intc.c
@@ -9,10 +9,16 @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/hw.h"
+#include "hw/sysbus.h"
 #include "hw/m68k/mcf.h"
 #include "exec/address-spaces.h"
 
+#define TYPE_MCF_INTC "mcf-intc"
+#define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
+
 typedef struct {
+    SysBusDevice parent_obj;
+
     MemoryRegion iomem;
     uint64_t ipr;
     uint64_t imr;
@@ -138,8 +144,10 @@ static void mcf_intc_set_irq(void *opaque, int irq, int level)
     mcf_intc_update(s);
 }
 
-static void mcf_intc_reset(mcf_intc_state *s)
+static void mcf_intc_reset(DeviceState *dev)
 {
+    mcf_intc_state *s = MCF_INTC(dev);
+
     s->imr = ~0ull;
     s->ipr = 0;
     s->ifr = 0;
@@ -154,17 +162,49 @@ static const MemoryRegionOps mcf_intc_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
+static void mcf_intc_instance_init(Object *obj)
+{
+    mcf_intc_state *s = MCF_INTC(obj);
+
+    memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
+}
+
+static void mcf_intc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+    dc->reset = mcf_intc_reset;
+}
+
+static const TypeInfo mcf_intc_gate_info = {
+    .name          = TYPE_MCF_INTC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(mcf_intc_state),
+    .instance_init = mcf_intc_instance_init,
+    .class_init    = mcf_intc_class_init,
+};
+
+static void mcf_intc_register_types(void)
+{
+    type_register_static(&mcf_intc_gate_info);
+}
+
+type_init(mcf_intc_register_types)
+
 qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
                         hwaddr base,
                         M68kCPU *cpu)
 {
+    DeviceState  *dev;
     mcf_intc_state *s;
 
-    s = g_malloc0(sizeof(mcf_intc_state));
+    dev = qdev_create(NULL, TYPE_MCF_INTC);
+    qdev_init_nofail(dev);
+
+    s = MCF_INTC(dev);
     s->cpu = cpu;
-    mcf_intc_reset(s);
 
-    memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
     memory_region_add_subregion(sysmem, base, &s->iomem);
 
     return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
-- 
2.7.4

Re: [Qemu-devel] [PATCH 1/2] hw/m68k: QOMify the ColdFire interrupt controller

[Laurent Vivier]

Le 12/02/2017 à 23:50, Thomas Huth a écrit :
> Use type_init() and friends to adapt the ColdFire interrupt
> controller to the latest QEMU device conventions.
> 
> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
> ---
>  hw/m68k/mcf_intc.c | 48 ++++++++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 44 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c
> index cf58132..8198afa 100644
> --- a/hw/m68k/mcf_intc.c
> +++ b/hw/m68k/mcf_intc.c
> @@ -9,10 +9,16 @@
>  #include "qemu-common.h"
>  #include "cpu.h"
>  #include "hw/hw.h"
> +#include "hw/sysbus.h"
>  #include "hw/m68k/mcf.h"
>  #include "exec/address-spaces.h"
>  
> +#define TYPE_MCF_INTC "mcf-intc"
> +#define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
> +
>  typedef struct {
> +    SysBusDevice parent_obj;
> +
>      MemoryRegion iomem;
>      uint64_t ipr;
>      uint64_t imr;
> @@ -138,8 +144,10 @@ static void mcf_intc_set_irq(void *opaque, int irq, int level)
>      mcf_intc_update(s);
>  }
>  
> -static void mcf_intc_reset(mcf_intc_state *s)
> +static void mcf_intc_reset(DeviceState *dev)
>  {
> +    mcf_intc_state *s = MCF_INTC(dev);
> +
>      s->imr = ~0ull;
>      s->ipr = 0;
>      s->ifr = 0;
> @@ -154,17 +162,49 @@ static const MemoryRegionOps mcf_intc_ops = {
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> +static void mcf_intc_instance_init(Object *obj)
> +{
> +    mcf_intc_state *s = MCF_INTC(obj);
> +
> +    memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
> +}
> +
> +static void mcf_intc_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
> +    dc->reset = mcf_intc_reset;
> +}
> +
> +static const TypeInfo mcf_intc_gate_info = {
> +    .name          = TYPE_MCF_INTC,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(mcf_intc_state),
> +    .instance_init = mcf_intc_instance_init,
> +    .class_init    = mcf_intc_class_init,
> +};
> +
> +static void mcf_intc_register_types(void)
> +{
> +    type_register_static(&mcf_intc_gate_info);
> +}
> +
> +type_init(mcf_intc_register_types)
> +
>  qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
>                          hwaddr base,
>                          M68kCPU *cpu)
>  {
> +    DeviceState  *dev;
>      mcf_intc_state *s;
>  
> -    s = g_malloc0(sizeof(mcf_intc_state));
> +    dev = qdev_create(NULL, TYPE_MCF_INTC);
> +    qdev_init_nofail(dev);
> +
> +    s = MCF_INTC(dev);
>      s->cpu = cpu;
> -    mcf_intc_reset(s);
>  
> -    memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
>      memory_region_add_subregion(sysmem, base, &s->iomem);
>  
>      return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
> 

Reviewed-by: Laurent Vivier <laurent@vivier.eu>

Later, we should consider to move this to mcf5208.c and to use
sysbus_mmio_map()/qdev_get_gpio_in().

Laurent

[Qemu-devel] [PATCH 2/2] MAINTAINERS: Add odd fixer the ColdFire boards

[Thomas Huth]

I did some work with real ColdFire boards in the past, and after
QOMifying most of the ColdFire devices recently, too, I feel confident
that I could at least take care of odd fixes for these boards.

Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
 MAINTAINERS | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7afbada..4fb2ed0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -561,7 +561,8 @@ F: hw/lm32/milkymist.c
 M68K Machines
 -------------
 an5206
-S: Orphan
+M: Thomas Huth <huth@tuxfamily.org>
+S: Odd Fixes
 F: hw/m68k/an5206.c
 F: hw/m68k/mcf5206.c
 
@@ -570,11 +571,13 @@ S: Orphan
 F: hw/m68k/dummy_m68k.c
 
 mcf5208
-S: Orphan
+M: Thomas Huth <huth@tuxfamily.org>
+S: Odd Fixes
 F: hw/m68k/mcf5208.c
 F: hw/m68k/mcf_intc.c
 F: hw/char/mcf_uart.c
 F: hw/net/mcf_fec.c
+F: include/hw/m68k/mcf*.h
 
 MicroBlaze Machines
 -------------------
-- 
2.7.4