[Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues

[Marcel Apfelbaum <marcel@redhat.com>]

v1 -> v2:
  - Added compat properties (Michael S. Tsirkin)
  - Rebased on latest master
  - Regarding the patch 1/4, we don't need to init the PCI "standard"
    config capabilities to 0 since they are "protected" by the Capabilities List bit
   (bit 4) to indicate that the Capabilities Pointer is located at offset 34h.


Fix a few issues found while running WHQL tests:

 - Assertion 1F27399E-30B9-44BC-8908-D6E6F3836212: FAILED. Enhanced Capability Header register
   of the PCI Express Enhanced Capabilities Absent Indicator table must be read-only .

   Solved in patch 1/4

 - Assertion 47C39833-84AD-44EA-9723-0695202ADDEA: FAILED. Bit 0 (Correctable Error Reporting Enable)
   in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
 - Assertion 5CBA2A63-A48E-4443-85FA-A7DCD8EA47BC: FAILED. Bit 1 (Non-Fatal Error Reporting Enable)
   in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
 - Assertion 0AB06F7C-59CB-4F9A-8363-B51B1ACAB54F: FAILED. Bit 2 (Fatal Error Reporting Enable)
   in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
 - Assertion E3834E4A-A7BD-410C-9A61-FA91770D2A71: FAILED. Bit 3 (Unsupported Request Reporting Enable)
   in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable 

   Solved in patch 2/4

 - Assertion 1587DC0B-FE59-494E-85B5-C2A59D0CC098: FAILED. Bit 6 (Common Clock Configuration)
   in the Link Control register (offset 10h) in the PCI Express Capability table must be read-writable .
 - Assertion 13DD25A3-07E4-4477-BE0F-2273BBB32174: FAILED. Bit 7 (Extended Synch) in the Link Control
   register (offset 10h) in the PCI Express Capability table must be read-writable .

  Solved in patch 3/4

  - AM Assertion 06779BD9-0C35-4CA1-9EB3-96E7DA9A74F8: FAILED. Bit range 1:0 (PowerState)in
    the Power Management Control/Status register (offset 4h) in the Power Management Capability table is 0h.
    It must be 3h after a supported D3 transition. 

Thanks,
Marcel

Marcel Apfelbaum (4):
  hw/pcie: fix Extended Configuration Space for devices with no Extended
    Capabilities
  hw/virtio: fix error enabling flags in Device Control register
  hw/virtio: fix Link Control Register for PCI Express virtio devices
  hw/virtio: fix Power Management Control Register for PCI Express
    virtio devices

 hw/pci/pci.c           |  2 ++
 hw/pci/pcie.c          | 20 ++++++++++++++++++++
 hw/virtio/virtio-pci.c | 31 +++++++++++++++++++++++++++++++
 hw/virtio/virtio-pci.h | 12 ++++++++++++
 include/hw/compat.h    | 16 ++++++++++++++++
 include/hw/pci/pci.h   |  2 ++
 include/hw/pci/pcie.h  |  5 +++++
 7 files changed, 88 insertions(+)

-- 
2.5.5