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From: Marcel Apfelbaum <marcel@redhat.com>
To: qemu-devel@nongnu.org
Cc: mst@redhat.com, marcel@redhat.com
Subject: [Qemu-devel] [PATCH V2 2/4] hw/virtio: fix error enabling flags in Device Control register
Date: Mon, 20 Feb 2017 22:43:11 +0200	[thread overview]
Message-ID: <1487623393-2492-3-git-send-email-marcel@redhat.com> (raw)
In-Reply-To: <1487623393-2492-1-git-send-email-marcel@redhat.com>

When the virtio devices are PCI Express, make error-enabling flags
writable to respect the PCIe spec.

Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
 hw/virtio/virtio-pci.c | 12 ++++++++++++
 hw/virtio/virtio-pci.h |  4 ++++
 include/hw/compat.h    |  4 ++++
 3 files changed, 20 insertions(+)

diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 5ce42af..9e2bca6 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1819,6 +1819,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
          */
         pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
 
+        if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
+            /* Init error enabling flags */
+            pcie_cap_deverr_init(pci_dev);
+        }
+
         if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
             pcie_ats_init(pci_dev, 256);
         }
@@ -1849,6 +1854,7 @@ static void virtio_pci_reset(DeviceState *qdev)
 {
     VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
     VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
+    PCIDevice *dev = PCI_DEVICE(qdev);
     int i;
 
     virtio_pci_stop_ioeventfd(proxy);
@@ -1858,6 +1864,10 @@ static void virtio_pci_reset(DeviceState *qdev)
     for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
         proxy->vqs[i].enabled = 0;
     }
+
+    if (pci_is_express(dev)) {
+        pcie_cap_deverr_reset(dev);
+    }
 }
 
 static Property virtio_pci_properties[] = {
@@ -1878,6 +1888,8 @@ static Property virtio_pci_properties[] = {
                      ignore_backend_features, false),
     DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
                     VIRTIO_PCI_FLAG_ATS_BIT, false),
+    DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
+                    VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index d00064c..120661d 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -73,6 +73,7 @@ enum {
     VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
     VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
     VIRTIO_PCI_FLAG_ATS_BIT,
+    VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
 };
 
 /* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -100,6 +101,9 @@ enum {
 /* address space translation service */
 #define VIRTIO_PCI_FLAG_ATS (1 << VIRTIO_PCI_FLAG_ATS_BIT)
 
+/* Init error enabling flags */
+#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT)
+
 typedef struct {
     MSIMessage msg;
     int virq;
diff --git a/include/hw/compat.h b/include/hw/compat.h
index ce3bfe3..c98776a 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -22,6 +22,10 @@
         .driver   = TYPE_PCI_DEVICE,\
         .property = "x-pcie-extcap-init",\
         .value    = "off",\
+    },{\
+        .driver   = "virtio-pci",\
+        .property = "x-pcie-deverr-init",\
+        .value    = "off",\
     },
 
 #define HW_COMPAT_2_7 \
-- 
2.5.5

  parent reply	other threads:[~2017-02-20 20:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities Marcel Apfelbaum
2017-02-20 20:43 ` Marcel Apfelbaum [this message]
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 4/4] hw/virtio: fix Power Management " Marcel Apfelbaum
2017-03-02  6:25 ` [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
2017-03-15 19:53   ` Marcel Apfelbaum

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