* [Qemu-devel] [PATCH V2 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
@ 2017-02-20 20:43 ` Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 2/4] hw/virtio: fix error enabling flags in Device Control register Marcel Apfelbaum
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-02-20 20:43 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel
Absence of any Extended Capabilities is required to be
indicated by an Extended Capability header with a Capability ID of
0000h, a Capability Version of 0h, and a Next Capability Offset of 000h.
Instead of inserting a 'NULL' capability is simpler to mark the start
of the Extended Configuration Space as read-only to achieve the same
behaviour.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/pci/pci.c | 2 ++
hw/pci/pcie.c | 6 ++++++
include/hw/compat.h | 4 ++++
include/hw/pci/pci.h | 2 ++
4 files changed, 14 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index a563555..4d2c0e1 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -64,6 +64,8 @@ static Property pci_props[] = {
QEMU_PCI_CAP_SERR_BITNR, true),
DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
+ DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
+ QEMU_PCIE_EXTCAP_INIT_BITNR, true),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index cbd4bb4..2526e3a 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -109,6 +109,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
+
+ if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
+ /* read-only to behave like a 'NULL' Extended Capability Header */
+ pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
+ }
+
return pos;
}
diff --git a/include/hw/compat.h b/include/hw/compat.h
index b7db438..ce3bfe3 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -18,6 +18,10 @@
.driver = "pci-bridge",\
.property = "shpc",\
.value = "on",\
+ },{\
+ .driver = TYPE_PCI_DEVICE,\
+ .property = "x-pcie-extcap-init",\
+ .value = "off",\
},
#define HW_COMPAT_2_7 \
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index cbc1fdf..ded978c 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -182,6 +182,8 @@ enum {
/* Link active status in endpoint capability is always set */
#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
+#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
+ QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
--
2.5.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH V2 2/4] hw/virtio: fix error enabling flags in Device Control register
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities Marcel Apfelbaum
@ 2017-02-20 20:43 ` Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices Marcel Apfelbaum
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-02-20 20:43 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel
When the virtio devices are PCI Express, make error-enabling flags
writable to respect the PCIe spec.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/virtio/virtio-pci.c | 12 ++++++++++++
hw/virtio/virtio-pci.h | 4 ++++
include/hw/compat.h | 4 ++++
3 files changed, 20 insertions(+)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 5ce42af..9e2bca6 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1819,6 +1819,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
*/
pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
+ if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
+ /* Init error enabling flags */
+ pcie_cap_deverr_init(pci_dev);
+ }
+
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
pcie_ats_init(pci_dev, 256);
}
@@ -1849,6 +1854,7 @@ static void virtio_pci_reset(DeviceState *qdev)
{
VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
+ PCIDevice *dev = PCI_DEVICE(qdev);
int i;
virtio_pci_stop_ioeventfd(proxy);
@@ -1858,6 +1864,10 @@ static void virtio_pci_reset(DeviceState *qdev)
for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
proxy->vqs[i].enabled = 0;
}
+
+ if (pci_is_express(dev)) {
+ pcie_cap_deverr_reset(dev);
+ }
}
static Property virtio_pci_properties[] = {
@@ -1878,6 +1888,8 @@ static Property virtio_pci_properties[] = {
ignore_backend_features, false),
DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_ATS_BIT, false),
+ DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index d00064c..120661d 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -73,6 +73,7 @@ enum {
VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
VIRTIO_PCI_FLAG_ATS_BIT,
+ VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -100,6 +101,9 @@ enum {
/* address space translation service */
#define VIRTIO_PCI_FLAG_ATS (1 << VIRTIO_PCI_FLAG_ATS_BIT)
+/* Init error enabling flags */
+#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
diff --git a/include/hw/compat.h b/include/hw/compat.h
index ce3bfe3..c98776a 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -22,6 +22,10 @@
.driver = TYPE_PCI_DEVICE,\
.property = "x-pcie-extcap-init",\
.value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-deverr-init",\
+ .value = "off",\
},
#define HW_COMPAT_2_7 \
--
2.5.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH V2 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 2/4] hw/virtio: fix error enabling flags in Device Control register Marcel Apfelbaum
@ 2017-02-20 20:43 ` Marcel Apfelbaum
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 4/4] hw/virtio: fix Power Management " Marcel Apfelbaum
2017-03-02 6:25 ` [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
4 siblings, 0 replies; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-02-20 20:43 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel
Make several Link Control Register flags writable to conform
with the PCI Express spec.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/pci/pcie.c | 14 ++++++++++++++
hw/virtio/virtio-pci.c | 8 ++++++++
hw/virtio/virtio-pci.h | 4 ++++
include/hw/compat.h | 4 ++++
include/hw/pci/pcie.h | 3 +++
5 files changed, 33 insertions(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 2526e3a..1804163 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -223,6 +223,20 @@ void pcie_cap_deverr_reset(PCIDevice *dev)
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
}
+void pcie_cap_lnkctl_init(PCIDevice *dev)
+{
+ uint32_t pos = dev->exp.exp_cap;
+ pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
+ PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
+}
+
+void pcie_cap_lnkctl_reset(PCIDevice *dev)
+{
+ uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
+ pci_long_test_and_clear_mask(lnkctl,
+ PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
+}
+
static void hotplug_event_update_event_status(PCIDevice *dev)
{
uint32_t pos = dev->exp.exp_cap;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 9e2bca6..1fb0a03 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1824,6 +1824,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
pcie_cap_deverr_init(pci_dev);
}
+ if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
+ /* Init Link Control Register */
+ pcie_cap_lnkctl_init(pci_dev);
+ }
+
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
pcie_ats_init(pci_dev, 256);
}
@@ -1867,6 +1872,7 @@ static void virtio_pci_reset(DeviceState *qdev)
if (pci_is_express(dev)) {
pcie_cap_deverr_reset(dev);
+ pcie_cap_lnkctl_reset(dev);
}
}
@@ -1890,6 +1896,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_ATS_BIT, false),
DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
+ DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index 120661d..9b5dd5a 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -74,6 +74,7 @@ enum {
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
VIRTIO_PCI_FLAG_ATS_BIT,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
+ VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -104,6 +105,9 @@ enum {
/* Init error enabling flags */
#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT)
+/* Init Link Control register */
+#define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
diff --git a/include/hw/compat.h b/include/hw/compat.h
index c98776a..0931aa5 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -26,6 +26,10 @@
.driver = "virtio-pci",\
.property = "x-pcie-deverr-init",\
.value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-lnkctl-init",\
+ .value = "off",\
},
#define HW_COMPAT_2_7 \
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index 163c519..11c6247 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -96,6 +96,9 @@ uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
void pcie_cap_deverr_init(PCIDevice *dev);
void pcie_cap_deverr_reset(PCIDevice *dev);
+void pcie_cap_lnkctl_init(PCIDevice *dev);
+void pcie_cap_lnkctl_reset(PCIDevice *dev);
+
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
void pcie_cap_slot_reset(PCIDevice *dev);
void pcie_cap_slot_write_config(PCIDevice *dev,
--
2.5.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH V2 4/4] hw/virtio: fix Power Management Control Register for PCI Express virtio devices
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
` (2 preceding siblings ...)
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices Marcel Apfelbaum
@ 2017-02-20 20:43 ` Marcel Apfelbaum
2017-03-02 6:25 ` [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
4 siblings, 0 replies; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-02-20 20:43 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel
Make Power Management State flag writable to conform
with the PCI Express spec.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/virtio/virtio-pci.c | 11 +++++++++++
hw/virtio/virtio-pci.h | 4 ++++
include/hw/compat.h | 4 ++++
include/hw/pci/pcie.h | 2 ++
4 files changed, 21 insertions(+)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 1fb0a03..fb86e58 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1812,6 +1812,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);
assert(pos > 0);
+ pci_dev->exp.pm_cap = pos;
/*
* Indicates that this function complies with revision 1.2 of the
@@ -1829,6 +1830,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
pcie_cap_lnkctl_init(pci_dev);
}
+ if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
+ /* Init Power Management Control Register */
+ pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
+ PCI_PM_CTRL_STATE_MASK);
+ }
+
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
pcie_ats_init(pci_dev, 256);
}
@@ -1873,6 +1880,8 @@ static void virtio_pci_reset(DeviceState *qdev)
if (pci_is_express(dev)) {
pcie_cap_deverr_reset(dev);
pcie_cap_lnkctl_reset(dev);
+
+ pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
}
}
@@ -1898,6 +1907,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
+ DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index 9b5dd5a..b095dfc 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -75,6 +75,7 @@ enum {
VIRTIO_PCI_FLAG_ATS_BIT,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
+ VIRTIO_PCI_FLAG_INIT_PM_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -108,6 +109,9 @@ enum {
/* Init Link Control register */
#define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT)
+/* Init Power Management */
+#define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 0931aa5..90606f9 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -30,6 +30,10 @@
.driver = "virtio-pci",\
.property = "x-pcie-lnkctl-init",\
.value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-pm-init",\
+ .value = "off",\
},
#define HW_COMPAT_2_7 \
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index 11c6247..3d8f24b 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -63,6 +63,8 @@ typedef enum {
struct PCIExpressDevice {
/* Offset of express capability in config space */
uint8_t exp_cap;
+ /* Offset of Power Management capability in config space */
+ uint8_t pm_cap;
/* SLOT */
bool hpev_notified; /* Logical AND of conditions for hot plug event.
--
2.5.5
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues
2017-02-20 20:43 [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
` (3 preceding siblings ...)
2017-02-20 20:43 ` [Qemu-devel] [PATCH V2 4/4] hw/virtio: fix Power Management " Marcel Apfelbaum
@ 2017-03-02 6:25 ` Marcel Apfelbaum
2017-03-15 19:53 ` Marcel Apfelbaum
4 siblings, 1 reply; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-03-02 6:25 UTC (permalink / raw)
To: qemu-devel; +Cc: mst
On 02/20/2017 10:43 PM, Marcel Apfelbaum wrote:
> v1 -> v2:
> - Added compat properties (Michael S. Tsirkin)
> - Rebased on latest master
> - Regarding the patch 1/4, we don't need to init the PCI "standard"
> config capabilities to 0 since they are "protected" by the Capabilities List bit
> (bit 4) to indicate that the Capabilities Pointer is located at offset 34h.
>
>
> Fix a few issues found while running WHQL tests:
>
ping
Thanks,
Marcel
> - Assertion 1F27399E-30B9-44BC-8908-D6E6F3836212: FAILED. Enhanced Capability Header register
> of the PCI Express Enhanced Capabilities Absent Indicator table must be read-only .
>
> Solved in patch 1/4
>
> - Assertion 47C39833-84AD-44EA-9723-0695202ADDEA: FAILED. Bit 0 (Correctable Error Reporting Enable)
> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
> - Assertion 5CBA2A63-A48E-4443-85FA-A7DCD8EA47BC: FAILED. Bit 1 (Non-Fatal Error Reporting Enable)
> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
> - Assertion 0AB06F7C-59CB-4F9A-8363-B51B1ACAB54F: FAILED. Bit 2 (Fatal Error Reporting Enable)
> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
> - Assertion E3834E4A-A7BD-410C-9A61-FA91770D2A71: FAILED. Bit 3 (Unsupported Request Reporting Enable)
> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable
>
> Solved in patch 2/4
>
> - Assertion 1587DC0B-FE59-494E-85B5-C2A59D0CC098: FAILED. Bit 6 (Common Clock Configuration)
> in the Link Control register (offset 10h) in the PCI Express Capability table must be read-writable .
> - Assertion 13DD25A3-07E4-4477-BE0F-2273BBB32174: FAILED. Bit 7 (Extended Synch) in the Link Control
> register (offset 10h) in the PCI Express Capability table must be read-writable .
>
> Solved in patch 3/4
>
> - AM Assertion 06779BD9-0C35-4CA1-9EB3-96E7DA9A74F8: FAILED. Bit range 1:0 (PowerState)in
> the Power Management Control/Status register (offset 4h) in the Power Management Capability table is 0h.
> It must be 3h after a supported D3 transition.
>
> Thanks,
> Marcel
>
> Marcel Apfelbaum (4):
> hw/pcie: fix Extended Configuration Space for devices with no Extended
> Capabilities
> hw/virtio: fix error enabling flags in Device Control register
> hw/virtio: fix Link Control Register for PCI Express virtio devices
> hw/virtio: fix Power Management Control Register for PCI Express
> virtio devices
>
> hw/pci/pci.c | 2 ++
> hw/pci/pcie.c | 20 ++++++++++++++++++++
> hw/virtio/virtio-pci.c | 31 +++++++++++++++++++++++++++++++
> hw/virtio/virtio-pci.h | 12 ++++++++++++
> include/hw/compat.h | 16 ++++++++++++++++
> include/hw/pci/pci.h | 2 ++
> include/hw/pci/pcie.h | 5 +++++
> 7 files changed, 88 insertions(+)
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues
2017-03-02 6:25 ` [Qemu-devel] [PATCH V2 0/4] hw/virtio: fix several PCI Express compliance issues Marcel Apfelbaum
@ 2017-03-15 19:53 ` Marcel Apfelbaum
0 siblings, 0 replies; 7+ messages in thread
From: Marcel Apfelbaum @ 2017-03-15 19:53 UTC (permalink / raw)
To: qemu-devel, mst
On 03/02/2017 08:25 AM, Marcel Apfelbaum wrote:
> On 02/20/2017 10:43 PM, Marcel Apfelbaum wrote:
>> v1 -> v2:
>> - Added compat properties (Michael S. Tsirkin)
>> - Rebased on latest master
>> - Regarding the patch 1/4, we don't need to init the PCI "standard"
>> config capabilities to 0 since they are "protected" by the Capabilities List bit
>> (bit 4) to indicate that the Capabilities Pointer is located at offset 34h.
>>
>>
>> Fix a few issues found while running WHQL tests:
>>
>
> ping
>
ping
Please add it to 2.9 please, the patches are ready for some time.
Thanks,
Marcel
> Thanks,
> Marcel
>
>> - Assertion 1F27399E-30B9-44BC-8908-D6E6F3836212: FAILED. Enhanced Capability Header register
>> of the PCI Express Enhanced Capabilities Absent Indicator table must be read-only .
>>
>> Solved in patch 1/4
>>
>> - Assertion 47C39833-84AD-44EA-9723-0695202ADDEA: FAILED. Bit 0 (Correctable Error Reporting Enable)
>> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
>> - Assertion 5CBA2A63-A48E-4443-85FA-A7DCD8EA47BC: FAILED. Bit 1 (Non-Fatal Error Reporting Enable)
>> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
>> - Assertion 0AB06F7C-59CB-4F9A-8363-B51B1ACAB54F: FAILED. Bit 2 (Fatal Error Reporting Enable)
>> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable .
>> - Assertion E3834E4A-A7BD-410C-9A61-FA91770D2A71: FAILED. Bit 3 (Unsupported Request Reporting Enable)
>> in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable
>>
>> Solved in patch 2/4
>>
>> - Assertion 1587DC0B-FE59-494E-85B5-C2A59D0CC098: FAILED. Bit 6 (Common Clock Configuration)
>> in the Link Control register (offset 10h) in the PCI Express Capability table must be read-writable .
>> - Assertion 13DD25A3-07E4-4477-BE0F-2273BBB32174: FAILED. Bit 7 (Extended Synch) in the Link Control
>> register (offset 10h) in the PCI Express Capability table must be read-writable .
>>
>> Solved in patch 3/4
>>
>> - AM Assertion 06779BD9-0C35-4CA1-9EB3-96E7DA9A74F8: FAILED. Bit range 1:0 (PowerState)in
>> the Power Management Control/Status register (offset 4h) in the Power Management Capability table is 0h.
>> It must be 3h after a supported D3 transition.
>>
>> Thanks,
>> Marcel
>>
>> Marcel Apfelbaum (4):
>> hw/pcie: fix Extended Configuration Space for devices with no Extended
>> Capabilities
>> hw/virtio: fix error enabling flags in Device Control register
>> hw/virtio: fix Link Control Register for PCI Express virtio devices
>> hw/virtio: fix Power Management Control Register for PCI Express
>> virtio devices
>>
>> hw/pci/pci.c | 2 ++
>> hw/pci/pcie.c | 20 ++++++++++++++++++++
>> hw/virtio/virtio-pci.c | 31 +++++++++++++++++++++++++++++++
>> hw/virtio/virtio-pci.h | 12 ++++++++++++
>> include/hw/compat.h | 16 ++++++++++++++++
>> include/hw/pci/pci.h | 2 ++
>> include/hw/pci/pcie.h | 5 +++++
>> 7 files changed, 88 insertions(+)
>>
>
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