From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction
Date: Wed, 22 Feb 2017 14:59:44 +0530 [thread overview]
Message-ID: <1487755788-16415-8-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1487755788-16415-1-git-send-email-nikunj@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 74185ba..eecdfe9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1483,7 +1483,10 @@ static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
static void gen_neg(DisasContext *ctx)
{
- gen_op_arith_neg(ctx, 0);
+ tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ }
}
static void gen_nego(DisasContext *ctx)
--
2.7.4
next prev parent reply other threads:[~2017-02-22 9:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 9:29 [Qemu-devel] [PATCH v2 00/11] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 01/11] target/ppc: move cpu_[read, write]_xer to cpu.c Nikunj A Dadhania
2017-02-22 10:26 ` Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 02/11] target/ppc: optimize gen_write_xer() Nikunj A Dadhania
2017-02-22 10:27 ` Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 03/11] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-22 10:31 ` Richard Henderson
2017-02-22 10:55 ` Nikunj A Dadhania
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-22 10:33 ` Richard Henderson
2017-02-22 10:37 ` Nikunj A Dadhania
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract Nikunj A Dadhania
2017-02-22 10:36 ` Richard Henderson
2017-02-22 10:58 ` Nikunj A Dadhania
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-22 10:37 ` Richard Henderson
2017-02-22 11:00 ` Nikunj A Dadhania
2017-02-22 9:29 ` Nikunj A Dadhania [this message]
2017-02-22 10:37 ` [Qemu-devel] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego Nikunj A Dadhania
2017-02-22 10:39 ` Richard Henderson
2017-02-22 11:03 ` Nikunj A Dadhania
2017-02-22 17:13 ` Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 09/11] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-22 10:40 ` Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 10/11] target/ppc: add ov32 flag in divide operations Nikunj A Dadhania
2017-02-22 10:40 ` Richard Henderson
2017-02-22 9:29 ` [Qemu-devel] [PATCH v2 11/11] target/ppc: add mcrxrx instruction Nikunj A Dadhania
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