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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego
Date: Wed, 22 Feb 2017 14:59:45 +0530	[thread overview]
Message-ID: <1487755788-16415-9-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1487755788-16415-1-git-send-email-nikunj@linux.vnet.ibm.com>

For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV
and OV32 are set to 1.

For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are
set to 1.

Use the tcg-ops for negation (neg_tl) and drop gen_op_arith_neg() as
nego was the last user.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target/ppc/translate.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eecdfe9..2a9f508 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1473,14 +1473,6 @@ static void gen_subfic(DisasContext *ctx)
 }
 
 /* neg neg. nego nego. */
-static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
-{
-    TCGv zero = tcg_const_tl(0);
-    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
-                      zero, 0, 0, compute_ov, Rc(ctx->opcode));
-    tcg_temp_free(zero);
-}
-
 static void gen_neg(DisasContext *ctx)
 {
     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
@@ -1491,7 +1483,23 @@ static void gen_neg(DisasContext *ctx)
 
 static void gen_nego(DisasContext *ctx)
 {
-    gen_op_arith_neg(ctx, 1);
+    TCGv t0 = tcg_temp_new();
+    TCGv zero = tcg_const_tl(0);
+
+    if (NARROW_MODE(ctx)) {
+        tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)], INT32_MIN);
+    } else {
+        tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)], (target_ulong)INT64_MIN);
+    }
+
+    tcg_gen_setcond_tl(TCG_COND_EQ, cpu_ov, t0, zero);
+    tcg_gen_mov_tl(cpu_ov32, cpu_ov);
+    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+    if (unlikely(Rc(ctx->opcode))) {
+        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+    }
+    tcg_temp_free(t0);
+    tcg_temp_free(zero);
 }
 
 /***                            Integer logical                            ***/
-- 
2.7.4

  parent reply	other threads:[~2017-02-22  9:31 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-22  9:29 [Qemu-devel] [PATCH v2 00/11] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 01/11] target/ppc: move cpu_[read, write]_xer to cpu.c Nikunj A Dadhania
2017-02-22 10:26   ` Richard Henderson
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 02/11] target/ppc: optimize gen_write_xer() Nikunj A Dadhania
2017-02-22 10:27   ` Richard Henderson
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 03/11] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-22 10:31   ` Richard Henderson
2017-02-22 10:55     ` Nikunj A Dadhania
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-22 10:33   ` Richard Henderson
2017-02-22 10:37     ` Nikunj A Dadhania
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract Nikunj A Dadhania
2017-02-22 10:36   ` Richard Henderson
2017-02-22 10:58     ` Nikunj A Dadhania
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-22 10:37   ` Richard Henderson
2017-02-22 11:00     ` Nikunj A Dadhania
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction Nikunj A Dadhania
2017-02-22 10:37   ` Richard Henderson
2017-02-22  9:29 ` Nikunj A Dadhania [this message]
2017-02-22 10:39   ` [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego Richard Henderson
2017-02-22 11:03     ` Nikunj A Dadhania
2017-02-22 17:13       ` Richard Henderson
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 09/11] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-22 10:40   ` Richard Henderson
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 10/11] target/ppc: add ov32 flag in divide operations Nikunj A Dadhania
2017-02-22 10:40   ` Richard Henderson
2017-02-22  9:29 ` [Qemu-devel] [PATCH v2 11/11] target/ppc: add mcrxrx instruction Nikunj A Dadhania

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