From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract
Date: Wed, 22 Feb 2017 17:14:38 +0530 [thread overview]
Message-ID: <1487763883-4877-6-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1487763883-4877-1-git-send-email-nikunj@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9165450..f3f92aa 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -827,7 +827,12 @@ static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
}
t0 = tcg_temp_new();
- tcg_gen_xor_tl(t0, arg0, arg1);
+ if (sub) {
+ tcg_gen_not_tl(t0, arg0);
+ tcg_gen_xor_tl(t0, t0, arg1);
+ } else {
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ }
tcg_gen_xor_tl(t0, t0, res);
tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
tcg_temp_free(t0);
@@ -1378,17 +1383,22 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
zero = tcg_const_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
+ gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
tcg_temp_free(zero);
tcg_temp_free(inv1);
} else {
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
tcg_gen_sub_tl(t0, arg2, arg1);
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
}
} else if (add_ca) {
/* Since we're ignoring carry-out, we can simplify the
--
2.7.4
next prev parent reply other threads:[~2017-02-22 11:45 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 11:44 [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 01/10] target/ppc: move cpu_[read, write]_xer to cpu.c Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 02/10] target/ppc: optimize gen_write_xer() Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-22 17:17 ` Richard Henderson
2017-02-22 17:20 ` Richard Henderson
2017-02-23 6:40 ` Nikunj A Dadhania
2017-02-23 22:34 ` Richard Henderson
2017-02-23 22:53 ` David Gibson
2017-02-24 0:41 ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
2017-02-24 4:50 ` David Gibson
2017-02-24 6:30 ` Richard Henderson
2017-02-27 1:39 ` David Gibson
2017-02-23 3:21 ` [Qemu-devel] " David Gibson
2017-02-23 5:09 ` Nikunj A Dadhania
2017-02-23 5:32 ` David Gibson
2017-02-23 7:02 ` Nikunj A Dadhania
2017-02-23 9:29 ` David Gibson
2017-02-23 22:36 ` Richard Henderson
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 04/10] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-22 17:20 ` Richard Henderson
2017-02-22 11:44 ` Nikunj A Dadhania [this message]
2017-02-22 17:21 ` [Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract Richard Henderson
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-22 17:26 ` Richard Henderson
2017-02-23 4:46 ` Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 07/10] target/ppc: use tcg ops for neg instruction Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 08/10] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 09/10] target/ppc: add ov32 flag in divide operations Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 10/10] target/ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-23 3:27 ` [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15 David Gibson
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