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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v6 5/8] target/ppc: use tcg ops for neg instruction
Date: Mon, 27 Feb 2017 10:27:58 +0530	[thread overview]
Message-ID: <1488171481-21699-6-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1488171481-21699-1-git-send-email-nikunj@linux.vnet.ibm.com>

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target/ppc/translate.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 16f422f..d4d9941 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1483,7 +1483,10 @@ static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
 
 static void gen_neg(DisasContext *ctx)
 {
-    gen_op_arith_neg(ctx, 0);
+    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+    if (unlikely(Rc(ctx->opcode))) {
+        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+    }
 }
 
 static void gen_nego(DisasContext *ctx)
-- 
2.7.4

  parent reply	other threads:[~2017-02-27  4:58 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-27  4:57 [Qemu-devel] [PATCH v6 0/8] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-27  4:57 ` [Qemu-devel] [PATCH v6 1/8] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-27  4:57 ` [Qemu-devel] [PATCH v6 2/8] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-27  4:57 ` [Qemu-devel] [PATCH v6 3/8] target/ppc: update ca32 in arithmetic substract Nikunj A Dadhania
2017-02-27  4:57 ` [Qemu-devel] [PATCH v6 4/8] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-27  4:57 ` Nikunj A Dadhania [this message]
2017-02-27  4:57 ` [Qemu-devel] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-27  4:58 ` [Qemu-devel] [PATCH v6 7/8] target/ppc: add ov32 flag in divide operations Nikunj A Dadhania
2017-02-27  4:58 ` [Qemu-devel] [PATCH v6 8/8] target/ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-27 23:21 ` [Qemu-devel] [PATCH v6 0/8] POWER9 TCG enablements - part15 David Gibson

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