* [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand() Peter Maydell
` (30 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Marcin Chojnacki <marcinch7@gmail.com>
Recent vanilla Raspberry Pi kernels started to make use of
the hardware random number generator in BCM2835 SoC. As a
result, those kernels wouldn't work anymore under QEMU
but rather just freeze during the boot process.
This patch implements a trivial BCM2835 compatible RNG,
and adds it as a peripheral to BCM2835 platform, which
allows to boot a vanilla Raspberry Pi kernel under Qemu.
Changes since v1:
* Prevented guest from writing [31..20] bits in rng_status
* Removed redundant minimum_version_id_old
* Added field entries for the state
* Changed realize function to reset
Signed-off-by: Marcin Chojnacki <marcinch7@gmail.com>
Message-id: 20170210210857.47893-1-marcinch7@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/bcm2835_peripherals.h | 2 +
include/hw/misc/bcm2835_rng.h | 27 ++++++++
hw/arm/bcm2835_peripherals.c | 15 +++++
hw/misc/bcm2835_rng.c | 124 +++++++++++++++++++++++++++++++++++
5 files changed, 169 insertions(+)
create mode 100644 include/hw/misc/bcm2835_rng.h
create mode 100644 hw/misc/bcm2835_rng.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 898e4cc..57a4406 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,6 +42,7 @@ obj-$(CONFIG_OMAP) += omap_sdrc.o
obj-$(CONFIG_OMAP) += omap_tap.o
obj-$(CONFIG_RASPI) += bcm2835_mbox.o
obj-$(CONFIG_RASPI) += bcm2835_property.o
+obj-$(CONFIG_RASPI) += bcm2835_rng.o
obj-$(CONFIG_SLAVIO) += slavio_misc.o
obj-$(CONFIG_ZYNQ) += zynq_slcr.o
obj-$(CONFIG_ZYNQ) += zynq-xadc.o
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index e12ae37..31241c7 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -19,6 +19,7 @@
#include "hw/dma/bcm2835_dma.h"
#include "hw/intc/bcm2835_ic.h"
#include "hw/misc/bcm2835_property.h"
+#include "hw/misc/bcm2835_rng.h"
#include "hw/misc/bcm2835_mbox.h"
#include "hw/sd/sdhci.h"
@@ -41,6 +42,7 @@ typedef struct BCM2835PeripheralState {
BCM2835DMAState dma;
BCM2835ICState ic;
BCM2835PropertyState property;
+ BCM2835RngState rng;
BCM2835MboxState mboxes;
SDHCIState sdhci;
} BCM2835PeripheralState;
diff --git a/include/hw/misc/bcm2835_rng.h b/include/hw/misc/bcm2835_rng.h
new file mode 100644
index 0000000..41a531b
--- /dev/null
+++ b/include/hw/misc/bcm2835_rng.h
@@ -0,0 +1,27 @@
+/*
+ * BCM2835 Random Number Generator emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_RNG_H
+#define BCM2835_RNG_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_BCM2835_RNG "bcm2835-rng"
+#define BCM2835_RNG(obj) \
+ OBJECT_CHECK(BCM2835RngState, (obj), TYPE_BCM2835_RNG)
+
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+
+ uint32_t rng_ctrl;
+ uint32_t rng_status;
+} BCM2835RngState;
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 2e641a3..9ed22d5 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -86,6 +86,11 @@ static void bcm2835_peripherals_init(Object *obj)
object_property_add_const_link(OBJECT(&s->property), "dma-mr",
OBJECT(&s->gpu_bus_mr), &error_abort);
+ /* Random Number Generator */
+ object_initialize(&s->rng, sizeof(s->rng), TYPE_BCM2835_RNG);
+ object_property_add_child(obj, "rng", OBJECT(&s->rng), NULL);
+ qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default());
+
/* Extended Mass Media Controller */
object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI);
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
@@ -226,6 +231,16 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
+ /* Random Number Generator */
+ object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
+
/* Extended Mass Media Controller */
object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
&err);
diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c
new file mode 100644
index 0000000..2242bc5
--- /dev/null
+++ b/hw/misc/bcm2835_rng.c
@@ -0,0 +1,124 @@
+/*
+ * BCM2835 Random Number Generator emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/misc/bcm2835_rng.h"
+
+static uint64_t bcm2835_rng_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ BCM2835RngState *s = (BCM2835RngState *)opaque;
+ uint32_t res = 0;
+
+ assert(size == 4);
+
+ switch (offset) {
+ case 0x0: /* rng_ctrl */
+ res = s->rng_ctrl;
+ break;
+ case 0x4: /* rng_status */
+ res = s->rng_status | (1 << 24);
+ break;
+ case 0x8: /* rng_data */
+ res = rand();
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "bcm2835_rng_read: Bad offset %x\n",
+ (int)offset);
+ res = 0;
+ break;
+ }
+
+ return res;
+}
+
+static void bcm2835_rng_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ BCM2835RngState *s = (BCM2835RngState *)opaque;
+
+ assert(size == 4);
+
+ switch (offset) {
+ case 0x0: /* rng_ctrl */
+ s->rng_ctrl = value;
+ break;
+ case 0x4: /* rng_status */
+ /* we shouldn't let the guest write to bits [31..20] */
+ s->rng_status &= ~0xFFFFF; /* clear 20 lower bits */
+ s->rng_status |= value & 0xFFFFF; /* set them to new value */
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "bcm2835_rng_write: Bad offset %x\n",
+ (int)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps bcm2835_rng_ops = {
+ .read = bcm2835_rng_read,
+ .write = bcm2835_rng_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_bcm2835_rng = {
+ .name = TYPE_BCM2835_RNG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(rng_ctrl, BCM2835RngState),
+ VMSTATE_UINT32(rng_status, BCM2835RngState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void bcm2835_rng_init(Object *obj)
+{
+ BCM2835RngState *s = BCM2835_RNG(obj);
+
+ memory_region_init_io(&s->iomem, obj, &bcm2835_rng_ops, s,
+ TYPE_BCM2835_RNG, 0x10);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_rng_reset(DeviceState *dev)
+{
+ BCM2835RngState *s = BCM2835_RNG(dev);
+
+ s->rng_ctrl = 0;
+ s->rng_status = 0;
+}
+
+static void bcm2835_rng_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = bcm2835_rng_reset;
+ dc->vmsd = &vmstate_bcm2835_rng;
+}
+
+static TypeInfo bcm2835_rng_info = {
+ .name = TYPE_BCM2835_RNG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835RngState),
+ .class_init = bcm2835_rng_class_init,
+ .instance_init = bcm2835_rng_init,
+};
+
+static void bcm2835_rng_register_types(void)
+{
+ type_register_static(&bcm2835_rng_info);
+}
+
+type_init(bcm2835_rng_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value Peter Maydell
` (29 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Switch to using qcrypto_random_bytes() rather than rand() as
our source of randomness for the BCM2835 RNG.
If qcrypto_random_bytes() fails, we don't want to return the guest a
non-random value in case they're really using it for cryptographic
purposes, so the best we can do is a fatal error. This shouldn't
happen unless something's broken, though.
In theory we could implement this device's full FIFO and interrupt
semantics and then just stop filling the FIFO. That's a lot of work,
though, and doesn't really give a very nice diagnostic to the user
since the guest will just seem to hang.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
---
hw/misc/bcm2835_rng.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c
index 2242bc5..4d62143 100644
--- a/hw/misc/bcm2835_rng.c
+++ b/hw/misc/bcm2835_rng.c
@@ -9,8 +9,33 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qapi/error.h"
+#include "crypto/random.h"
#include "hw/misc/bcm2835_rng.h"
+static uint32_t get_random_bytes(void)
+{
+ uint32_t res;
+ Error *err = NULL;
+
+ if (qcrypto_random_bytes((uint8_t *)&res, sizeof(res), &err) < 0) {
+ /* On failure we don't want to return the guest a non-random
+ * value in case they're really using it for cryptographic
+ * purposes, so the best we can do is die here.
+ * This shouldn't happen unless something's broken.
+ * In theory we could implement this device's full FIFO
+ * and interrupt semantics and then just stop filling the
+ * FIFO. That's a lot of work, though, so we assume any
+ * errors are systematic problems and trust that if we didn't
+ * fail as the guest inited then we won't fail later on
+ * mid-run.
+ */
+ error_report_err(err);
+ exit(1);
+ }
+ return res;
+}
+
static uint64_t bcm2835_rng_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -27,7 +52,7 @@ static uint64_t bcm2835_rng_read(void *opaque, hwaddr offset,
res = s->rng_status | (1 << 24);
break;
case 0x8: /* rng_data */
- res = rand();
+ res = get_random_bytes();
break;
default:
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand() Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer Peter Maydell
` (28 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Prasad J Pandit <pjp@fedoraproject.org>
In SDHCI protocol, the transfer mode register is defined
to be of 6 bits. Mask its value with '0x0037' so that an
invalid value could not be assigned.
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20170214185225.7994-2-ppandit@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index da32b5f..a65c77d 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -119,6 +119,7 @@
(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
(SDHC_CAPAB_TOCLKFREQ))
+#define MASK_TRNMOD 0x0037
#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
static uint8_t sdhci_slotint(SDHCIState *s)
@@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
value &= ~SDHC_TRNS_DMA;
}
- MASKED_WRITE(s->trnmod, mask, value);
+ MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
/* Writing to the upper byte of CMDREG triggers SD command generation */
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke " Peter Maydell
` (27 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Prasad J Pandit <pjp@fedoraproject.org>
In the SDHCI protocol, the transfer mode register value
is used during multi block transfer to check if block count
register is enabled and should be updated. Transfer mode
register could be set such that, block count register would
not be updated, thus leading to an infinite loop. Add check
to avoid it.
Reported-by: Wjjzhang <wjjzhang@tencent.com>
Reported-by: Jiang Xin <jiangxin1@huawei.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-id: 20170214185225.7994-3-ppandit@redhat.com
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/sdhci.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a65c77d..5adeab6 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -487,6 +487,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
+ if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
+ qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
+ return;
+ }
+
/* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
* possible stop at page boundary if initial address is not page aligned,
* allow them to work properly */
@@ -798,11 +803,6 @@ static void sdhci_data_transfer(void *opaque)
if (s->trnmod & SDHC_TRNS_DMA) {
switch (SDHC_DMA_TYPE(s->hostctl)) {
case SDHC_CTRL_SDMA:
- if ((s->trnmod & SDHC_TRNS_MULTI) &&
- (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
- break;
- }
-
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
sdhci_sdma_transfer_single_block(s);
} else {
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers Peter Maydell
` (26 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Prasad J Pandit <pjp@fedoraproject.org>
In sdhci_write invoke multi block transfer if it is enabled
in the transfer mode register 's->trnmod'.
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-id: 20170214185225.7994-4-ppandit@redhat.com
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/sdhci.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 5adeab6..c270e09 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1023,7 +1023,11 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
/* Writing to last byte of sdmasysad might trigger transfer */
if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
- sdhci_sdma_transfer_multi_blocks(s);
+ if (s->trnmod & SDHC_TRNS_MULTI) {
+ sdhci_sdma_transfer_multi_blocks(s);
+ } else {
+ sdhci_sdma_transfer_single_block(s);
+ }
}
break;
case SDHC_BLKSIZE:
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke " Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak Peter Maydell
` (25 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Prasad J Pandit <pjp@fedoraproject.org>
In SDHCI protocol, the 'Block count enable' bit of the Transfer
Mode register is relevant only in multi block transfers. We need
not check it in single block transfers.
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-id: 20170214185225.7994-5-ppandit@redhat.com
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/sdhci.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index c270e09..6d6a791 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -570,7 +570,6 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
}
/* single block SDMA transfer */
-
static void sdhci_sdma_transfer_single_block(SDHCIState *s)
{
int n;
@@ -589,10 +588,7 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
}
}
-
- if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
- s->blkcnt--;
- }
+ s->blkcnt--;
sdhci_end_transfer(s);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions Peter Maydell
` (24 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Igor Mammedov <imammedo@redhat.com>
object_new(FOO) returns an object with ref_cnt == 1
and following
object_property_set_bool(cpuobj, true, "realized", NULL)
set parent of cpuobj to '/machine/unattached' which makes
ref_cnt == 2.
Since machvirt_init() doesn't take ownership of cpuobj
returned by object_new() it should explicitly drop
reference to cpuobj when dangling pointer is about to
go out of scope like it's done pc_new_cpu() to avoid
object leak.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 1487253461-269218-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f3440f2..0c270b8 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1378,6 +1378,7 @@ static void machvirt_init(MachineState *machine)
}
object_property_set_bool(cpuobj, true, "realized", NULL);
+ object_unref(cpuobj);
}
fdt_add_timer_nodes(vms);
fdt_add_cpu_nodes(vms);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns Peter Maydell
` (23 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Nick Reilly <nreilly@blackberry.com>
The aarch64 crypto instructions for AES and SHA are missing the
check for if the FPU is enabled.
Signed-off-by: Nick Reilly <nreilly@blackberry.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e15eae6..24de30d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10933,6 +10933,10 @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
/* Note that we convert the Vx register indexes into the
* index within the vfp.regs[] array, so we can share the
* helper with the AArch32 instructions.
@@ -10997,6 +11001,10 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
tcg_rd_regno = tcg_const_i32(rd << 1);
tcg_rn_regno = tcg_const_i32(rn << 1);
tcg_rm_regno = tcg_const_i32(rm << 1);
@@ -11060,6 +11068,10 @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
return;
}
+ if (!fp_access_check(s)) {
+ return;
+ }
+
tcg_rd_regno = tcg_const_i32(rd << 1);
tcg_rn_regno = tcg_const_i32(rn << 1);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation Peter Maydell
` (22 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
In get_page_addr_code(), if the guest PC doesn't correspond to RAM
then we currently run the CPU's do_unassigned_access() hook if it has
one, and otherwise we give up and exit QEMU with a more-or-less
useful message. This code assumes that the do_unassigned_access hook
will never return, because if it does then we'll plough on attempting
to use a non-RAM TLB entry to get a RAM address and will abort() in
qemu_ram_addr_from_host_nofail(). Unfortunately some CPU
implementations of this hook do return: Microblaze, SPARC and the ARM
v7M.
Change the code to call report_bad_exec() if the hook returns, as
well as if it didn't have one. This means we can tidy it up to use
the cpu_unassigned_access() function which wraps the "get the CPU
class and call the hook if it has one" work, since we aren't trying
to distinguish "no hook" from "hook existed and returned" any more.
This brings the handling of this hook into line with the handling
used for data accesses, where "hook returned" is treated the
same as "no hook existed" and gets you the default behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
cputlb.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 7fa7fef..f5d056c 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -769,14 +769,13 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
if (memory_region_is_unassigned(mr)) {
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->do_unassigned_access) {
- cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
- } else {
- report_bad_exec(cpu, addr);
- exit(1);
- }
+ cpu_unassigned_access(cpu, addr, false, true, 0, 4);
+ /* The CPU's unassigned access hook might have longjumped out
+ * with an exception. If it didn't (or there was no hook) then
+ * we can't proceed further.
+ */
+ report_bad_exec(cpu, addr);
+ exit(1);
}
p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
return qemu_ram_addr_from_host_nofail(p);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling Peter Maydell
` (21 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
In 2.9 ITS will block save/restore and migration use cases. As such,
let's introduce a user option that allows to turn its instantiation
off, along with GICv3. With the "its" option turned false, migration
will be possible, obviously at the expense of MSI support (with GICv3).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1487681108-14452-1-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/virt.h | 1 +
hw/arm/virt.c | 31 +++++++++++++++++++++++++++++--
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 58ce74e..33b0ff3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -93,6 +93,7 @@ typedef struct {
FWCfgState *fw_cfg;
bool secure;
bool highmem;
+ bool its;
bool virt;
int32_t gic_version;
struct arm_boot_info bootinfo;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0c270b8..5f62a03 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -535,7 +535,6 @@ static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
static void create_gic(VirtMachineState *vms, qemu_irq *pic)
{
/* We create a standalone GIC */
- VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
DeviceState *gicdev;
SysBusDevice *gicbusdev;
const char *gictype;
@@ -605,7 +604,7 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
fdt_add_gic_node(vms);
- if (type == 3 && !vmc->no_its) {
+ if (type == 3 && vms->its) {
create_its(vms, gicdev);
} else if (type == 2) {
create_v2m(vms, pic);
@@ -1481,6 +1480,20 @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
vms->highmem = value;
}
+static bool virt_get_its(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->its;
+}
+
+static void virt_set_its(Object *obj, bool value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->its = value;
+}
+
static char *virt_get_gic_version(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1541,6 +1554,7 @@ type_init(machvirt_machine_init);
static void virt_2_9_instance_init(Object *obj)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
/* EL3 is disabled by default on virt: this makes us consistent
* between KVM and TCG for this board, and it also allows us to
@@ -1580,6 +1594,19 @@ static void virt_2_9_instance_init(Object *obj)
"Set GIC version. "
"Valid values are 2, 3 and host", NULL);
+ if (vmc->no_its) {
+ vms->its = false;
+ } else {
+ /* Default allows ITS instantiation */
+ vms->its = true;
+ object_property_add_bool(obj, "its", virt_get_its,
+ virt_set_its, NULL);
+ object_property_set_description(obj, "its",
+ "Set on/off to enable/disable "
+ "ITS instantiation",
+ NULL);
+ }
+
vms->memmap = a15memmap;
vms->irqmap = a15irqmap;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState Peter Maydell
` (20 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Kurban Mallachiev <mallachiev@ispras.ru>
The i.MX timer device can be reset by writing to the SWR bit
of the CR register. This has to behave differently from hard
(power-on) reset because it does not reset all of the bits
in the CR register.
We were incorrectly implementing soft reset and hard reset
the same way, and in addition had a logic error which meant
that we were clearing the bits that soft-reset is supposed
to preserve and not touching the bits that soft-reset clears.
This was not correct behaviour for either kind of reset.
Separate out the soft reset and hard reset code paths, and
correct the handling of reset of the CR register so that it
is correct in both cases.
Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru>
[PMM: rephrased commit message, spacing on operators;
use bool rather than int for is_soft_reset]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/imx_gpt.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 010ccbf..4b9b54b 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -296,18 +296,23 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
return reg_value;
}
-static void imx_gpt_reset(DeviceState *dev)
-{
- IMXGPTState *s = IMX_GPT(dev);
+static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
+{
/* stop timer */
ptimer_stop(s->timer);
- /*
- * Soft reset doesn't touch some bits; hard reset clears them
+ /* Soft reset and hard reset differ only in their handling of the CR
+ * register -- soft reset preserves the values of some bits there.
*/
- s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
- GPT_CR_WAITEN|GPT_CR_DBGEN);
+ if (is_soft_reset) {
+ /* Clear all CR bits except those that are preserved by soft reset. */
+ s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN |
+ GPT_CR_WAITEN | GPT_CR_DBGEN |
+ (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT);
+ } else {
+ s->cr = 0;
+ }
s->sr = 0;
s->pr = 0;
s->ir = 0;
@@ -333,6 +338,18 @@ static void imx_gpt_reset(DeviceState *dev)
}
}
+static void imx_gpt_soft_reset(DeviceState *dev)
+{
+ IMXGPTState *s = IMX_GPT(dev);
+ imx_gpt_reset_common(s, true);
+}
+
+static void imx_gpt_reset(DeviceState *dev)
+{
+ IMXGPTState *s = IMX_GPT(dev);
+ imx_gpt_reset_common(s, false);
+}
+
static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
@@ -348,7 +365,7 @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
s->cr = value & ~0x7c14;
if (s->cr & GPT_CR_SWR) { /* force reset */
/* handle the reset */
- imx_gpt_reset(DEVICE(s));
+ imx_gpt_soft_reset(DEVICE(s));
} else {
/* set our freq, as the source might have changed */
imx_gpt_set_freq(s);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP Peter Maydell
` (19 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Rename the nvic_state struct to NVICState, to match
our naming conventions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 44 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index fe5c303..09975f3 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -21,7 +21,7 @@
#include "gic_internal.h"
#include "qemu/log.h"
-typedef struct {
+typedef struct NVICState {
GICState gic;
ARMCPU *cpu;
struct {
@@ -35,7 +35,7 @@ typedef struct {
MemoryRegion container;
uint32_t num_irq;
qemu_irq sysresetreq;
-} nvic_state;
+} NVICState;
#define TYPE_NVIC "armv7m_nvic"
/**
@@ -57,7 +57,7 @@ typedef struct NVICClass {
#define NVIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
#define NVIC(obj) \
- OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
static const uint8_t nvic_id[] = {
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
@@ -74,7 +74,7 @@ static const uint8_t nvic_id[] = {
int system_clock_scale;
/* Conversion factor from qemu timer to SysTick frequencies. */
-static inline int64_t systick_scale(nvic_state *s)
+static inline int64_t systick_scale(NVICState *s)
{
if (s->systick.control & SYSTICK_CLKSOURCE)
return system_clock_scale;
@@ -82,7 +82,7 @@ static inline int64_t systick_scale(nvic_state *s)
return 1000;
}
-static void systick_reload(nvic_state *s, int reset)
+static void systick_reload(NVICState *s, int reset)
{
/* The Cortex-M3 Devices Generic User Guide says that "When the
* ENABLE bit is set to 1, the counter loads the RELOAD value from the
@@ -101,7 +101,7 @@ static void systick_reload(nvic_state *s, int reset)
static void systick_timer_tick(void * opaque)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
s->systick.control |= SYSTICK_COUNTFLAG;
if (s->systick.control & SYSTICK_TICKINT) {
/* Trigger the interrupt. */
@@ -114,7 +114,7 @@ static void systick_timer_tick(void * opaque)
}
}
-static void systick_reset(nvic_state *s)
+static void systick_reset(NVICState *s)
{
s->systick.control = 0;
s->systick.reload = 0;
@@ -126,7 +126,7 @@ static void systick_reset(nvic_state *s)
IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
void armv7m_nvic_set_pending(void *opaque, int irq)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
if (irq >= 16)
irq += 16;
gic_set_pending_private(&s->gic, 0, irq);
@@ -135,7 +135,7 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
/* Make pending IRQ active. */
int armv7m_nvic_acknowledge_irq(void *opaque)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
uint32_t irq;
irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
@@ -148,13 +148,13 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
void armv7m_nvic_complete_irq(void *opaque, int irq)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
if (irq >= 16)
irq += 16;
gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
}
-static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
+static uint32_t nvic_readl(NVICState *s, uint32_t offset)
{
ARMCPU *cpu = s->cpu;
uint32_t val;
@@ -294,7 +294,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
}
}
-static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
+static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
{
ARMCPU *cpu = s->cpu;
uint32_t oldval;
@@ -425,7 +425,7 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
unsigned size)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
int i;
uint32_t val;
@@ -454,7 +454,7 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
static void nvic_sysreg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- nvic_state *s = (nvic_state *)opaque;
+ NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
int i;
@@ -486,17 +486,17 @@ static const VMStateDescription vmstate_nvic = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(systick.control, nvic_state),
- VMSTATE_UINT32(systick.reload, nvic_state),
- VMSTATE_INT64(systick.tick, nvic_state),
- VMSTATE_TIMER_PTR(systick.timer, nvic_state),
+ VMSTATE_UINT32(systick.control, NVICState),
+ VMSTATE_UINT32(systick.reload, NVICState),
+ VMSTATE_INT64(systick.tick, NVICState),
+ VMSTATE_TIMER_PTR(systick.timer, NVICState),
VMSTATE_END_OF_LIST()
}
};
static void armv7m_nvic_reset(DeviceState *dev)
{
- nvic_state *s = NVIC(dev);
+ NVICState *s = NVIC(dev);
NVICClass *nc = NVIC_GET_CLASS(s);
nc->parent_reset(dev);
/* Common GIC reset resets to disabled; the NVIC doesn't have
@@ -513,7 +513,7 @@ static void armv7m_nvic_reset(DeviceState *dev)
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
{
- nvic_state *s = NVIC(dev);
+ NVICState *s = NVIC(dev);
NVICClass *nc = NVIC_GET_CLASS(s);
Error *local_err = NULL;
@@ -569,7 +569,7 @@ static void armv7m_nvic_instance_init(Object *obj)
*/
GICState *s = ARM_GIC_COMMON(obj);
DeviceState *dev = DEVICE(obj);
- nvic_state *nvic = NVIC(obj);
+ NVICState *nvic = NVIC(obj);
/* The ARM v7m may have anything from 0 to 496 external interrupt
* IRQ lines. We default to 64. Other boards may differ and should
* set the num-irq property appropriately.
@@ -594,7 +594,7 @@ static const TypeInfo armv7m_nvic_info = {
.name = TYPE_NVIC,
.parent = TYPE_ARM_GIC_COMMON,
.instance_init = armv7m_nvic_instance_init,
- .instance_size = sizeof(nvic_state),
+ .instance_size = sizeof(NVICState),
.class_init = armv7m_nvic_class_init,
.class_size = sizeof(NVICClass),
};
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code Peter Maydell
` (18 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Add a state field for the v7M PRIGROUP register and implent
reading and writing it. The current NVIC doesn't honour
the values written, but the new version will.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 09975f3..ce22001 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -24,6 +24,9 @@
typedef struct NVICState {
GICState gic;
ARMCPU *cpu;
+
+ uint32_t prigroup;
+
struct {
uint32_t control;
uint32_t reload;
@@ -223,7 +226,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
case 0xd08: /* Vector Table Offset. */
return cpu->env.v7m.vecbase;
case 0xd0c: /* Application Interrupt/Reset Control. */
- return 0xfa050000;
+ return 0xfa050000 | (s->prigroup << 8);
case 0xd10: /* System Control. */
/* TODO: Implement SLEEPONEXIT. */
return 0;
@@ -362,9 +365,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
if (value & 1) {
qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
}
- if (value & 0x700) {
- qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n");
- }
+ s->prigroup = extract32(value, 8, 3);
}
break;
case 0xd10: /* System Control. */
@@ -483,13 +484,14 @@ static const MemoryRegionOps nvic_sysreg_ops = {
static const VMStateDescription vmstate_nvic = {
.name = "armv7m_nvic",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(systick.control, NVICState),
VMSTATE_UINT32(systick.reload, NVICState),
VMSTATE_INT64(systick.tick, NVICState),
VMSTATE_TIMER_PTR(systick.timer, NVICState),
+ VMSTATE_UINT32(prigroup, NVICState),
VMSTATE_END_OF_LIST()
}
};
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions Peter Maydell
` (17 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Michael Davidsaver <mdavidsaver@gmail.com>
Despite some superficial similarities of register layout, the
M-profile NVIC is really very different from the A-profile GIC.
Our current attempt to reuse the GIC code means that we have
significant bugs in our NVIC.
Implement the NVIC as an entirely separate device, to give
us somewhere we can get the behaviour correct.
This initial commit does not attempt to implement exception
priority escalation, since the GIC-based code didn't either.
It does fix a few bugs in passing:
* ICSR.RETTOBASE polarity was wrong and didn't account for
internal exceptions
* ICSR.VECTPENDING was 16 too high if the pending exception
was for an external interrupt
* UsageFault, BusFault and MemFault were not disabled on reset
as they are supposed to be
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
[PMM: reworked, various bugs and stylistic cleanups]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 738 ++++++++++++++++++++++++++++++++++++++++----------
hw/intc/trace-events | 15 +
2 files changed, 609 insertions(+), 144 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ce22001..fb4c985 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -17,48 +17,88 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/arm/arm.h"
+#include "target/arm/cpu.h"
#include "exec/address-spaces.h"
-#include "gic_internal.h"
#include "qemu/log.h"
+#include "trace.h"
+
+/* IRQ number counting:
+ *
+ * the num-irq property counts the number of external IRQ lines
+ *
+ * NVICState::num_irq counts the total number of exceptions
+ * (external IRQs, the 15 internal exceptions including reset,
+ * and one for the unused exception number 0).
+ *
+ * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
+ *
+ * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
+ *
+ * Iterating through all exceptions should typically be done with
+ * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
+ *
+ * The external qemu_irq lines are the NVIC's external IRQ lines,
+ * so line 0 is exception 16.
+ *
+ * In the terminology of the architecture manual, "interrupts" are
+ * a subcategory of exception referring to the external interrupts
+ * (which are exception numbers NVIC_FIRST_IRQ and upward).
+ * For historical reasons QEMU tends to use "interrupt" and
+ * "exception" more or less interchangeably.
+ */
+#define NVIC_FIRST_IRQ 16
+#define NVIC_MAX_VECTORS 512
+#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
+
+/* Effective running priority of the CPU when no exception is active
+ * (higher than the highest possible priority value)
+ */
+#define NVIC_NOEXC_PRIO 0x100
+
+typedef struct VecInfo {
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
+ * priority values for RESET, NMI and HardFault can be negative.
+ */
+ int16_t prio;
+ uint8_t enabled;
+ uint8_t pending;
+ uint8_t active;
+ uint8_t level; /* exceptions <=15 never set level */
+} VecInfo;
typedef struct NVICState {
- GICState gic;
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
ARMCPU *cpu;
+ VecInfo vectors[NVIC_MAX_VECTORS];
uint32_t prigroup;
+ /* vectpending and exception_prio are both cached state that can
+ * be recalculated from the vectors[] array and the prigroup field.
+ */
+ unsigned int vectpending; /* highest prio pending enabled exception */
+ int exception_prio; /* group prio of the highest prio active exception */
+
struct {
uint32_t control;
uint32_t reload;
int64_t tick;
QEMUTimer *timer;
} systick;
+
MemoryRegion sysregmem;
- MemoryRegion gic_iomem_alias;
MemoryRegion container;
+
uint32_t num_irq;
+ qemu_irq excpout;
qemu_irq sysresetreq;
} NVICState;
#define TYPE_NVIC "armv7m_nvic"
-/**
- * NVICClass:
- * @parent_reset: the parent class' reset handler.
- *
- * A model of the v7M NVIC and System Controller
- */
-typedef struct NVICClass {
- /*< private >*/
- ARMGICClass parent_class;
- /*< public >*/
- DeviceRealize parent_realize;
- void (*parent_reset)(DeviceState *dev);
-} NVICClass;
-
-#define NVIC_CLASS(klass) \
- OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
-#define NVIC_GET_CLASS(obj) \
- OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
+
#define NVIC(obj) \
OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
@@ -125,47 +165,283 @@ static void systick_reset(NVICState *s)
timer_del(s->systick.timer);
}
-/* The external routines use the hardware vector numbering, ie. the first
- IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
+static int nvic_pending_prio(NVICState *s)
+{
+ /* return the priority of the current pending interrupt,
+ * or NVIC_NOEXC_PRIO if no interrupt is pending
+ */
+ return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
+}
+
+/* Return the value of the ISCR RETTOBASE bit:
+ * 1 if there is exactly one active exception
+ * 0 if there is more than one active exception
+ * UNKNOWN if there are no active exceptions (we choose 1,
+ * which matches the choice Cortex-M3 is documented as making).
+ *
+ * NB: some versions of the documentation talk about this
+ * counting "active exceptions other than the one shown by IPSR";
+ * this is only different in the obscure corner case where guest
+ * code has manually deactivated an exception and is about
+ * to fail an exception-return integrity check. The definition
+ * above is the one from the v8M ARM ARM and is also in line
+ * with the behaviour documented for the Cortex-M3.
+ */
+static bool nvic_rettobase(NVICState *s)
+{
+ int irq, nhand = 0;
+
+ for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
+ if (s->vectors[irq].active) {
+ nhand++;
+ if (nhand == 2) {
+ return 0;
+ }
+ }
+ }
+
+ return 1;
+}
+
+/* Return the value of the ISCR ISRPENDING bit:
+ * 1 if an external interrupt is pending
+ * 0 if no external interrupt is pending
+ */
+static bool nvic_isrpending(NVICState *s)
+{
+ int irq;
+
+ /* We can shortcut if the highest priority pending interrupt
+ * happens to be external or if there is nothing pending.
+ */
+ if (s->vectpending > NVIC_FIRST_IRQ) {
+ return true;
+ }
+ if (s->vectpending == 0) {
+ return false;
+ }
+
+ for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
+ if (s->vectors[irq].pending) {
+ return true;
+ }
+ }
+ return false;
+}
+
+/* Return a mask word which clears the subpriority bits from
+ * a priority value for an M-profile exception, leaving only
+ * the group priority.
+ */
+static inline uint32_t nvic_gprio_mask(NVICState *s)
+{
+ return ~0U << (s->prigroup + 1);
+}
+
+/* Recompute vectpending and exception_prio */
+static void nvic_recompute_state(NVICState *s)
+{
+ int i;
+ int pend_prio = NVIC_NOEXC_PRIO;
+ int active_prio = NVIC_NOEXC_PRIO;
+ int pend_irq = 0;
+
+ for (i = 1; i < s->num_irq; i++) {
+ VecInfo *vec = &s->vectors[i];
+
+ if (vec->enabled && vec->pending && vec->prio < pend_prio) {
+ pend_prio = vec->prio;
+ pend_irq = i;
+ }
+ if (vec->active && vec->prio < active_prio) {
+ active_prio = vec->prio;
+ }
+ }
+
+ s->vectpending = pend_irq;
+ s->exception_prio = active_prio & nvic_gprio_mask(s);
+
+ trace_nvic_recompute_state(s->vectpending, s->exception_prio);
+}
+
+/* Return the current execution priority of the CPU
+ * (equivalent to the pseudocode ExecutionPriority function).
+ * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
+ */
+static inline int nvic_exec_prio(NVICState *s)
+{
+ CPUARMState *env = &s->cpu->env;
+ int running;
+
+ if (env->daif & PSTATE_F) { /* FAULTMASK */
+ running = -1;
+ } else if (env->daif & PSTATE_I) { /* PRIMASK */
+ running = 0;
+ } else if (env->v7m.basepri > 0) {
+ running = env->v7m.basepri & nvic_gprio_mask(s);
+ } else {
+ running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
+ }
+ /* consider priority of active handler */
+ return MIN(running, s->exception_prio);
+}
+
+/* caller must call nvic_irq_update() after this */
+static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
+{
+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
+ assert(irq < s->num_irq);
+
+ s->vectors[irq].prio = prio;
+
+ trace_nvic_set_prio(irq, prio);
+}
+
+/* Recompute state and assert irq line accordingly.
+ * Must be called after changes to:
+ * vec->active, vec->enabled, vec->pending or vec->prio for any vector
+ * prigroup
+ */
+static void nvic_irq_update(NVICState *s)
+{
+ int lvl;
+ int pend_prio;
+
+ nvic_recompute_state(s);
+ pend_prio = nvic_pending_prio(s);
+
+ /* Raise NVIC output if this IRQ would be taken, except that we
+ * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
+ * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
+ * to those CPU registers don't cause us to recalculate the NVIC
+ * pending info.
+ */
+ lvl = (pend_prio < s->exception_prio);
+ trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
+ qemu_set_irq(s->excpout, lvl);
+}
+
+static void armv7m_nvic_clear_pending(void *opaque, int irq)
+{
+ NVICState *s = (NVICState *)opaque;
+ VecInfo *vec;
+
+ assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
+
+ vec = &s->vectors[irq];
+ trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
+ if (vec->pending) {
+ vec->pending = 0;
+ nvic_irq_update(s);
+ }
+}
+
void armv7m_nvic_set_pending(void *opaque, int irq)
{
NVICState *s = (NVICState *)opaque;
- if (irq >= 16)
- irq += 16;
- gic_set_pending_private(&s->gic, 0, irq);
+ VecInfo *vec;
+
+ assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
+
+ vec = &s->vectors[irq];
+ trace_nvic_set_pending(irq, vec->enabled, vec->prio);
+ if (!vec->pending) {
+ vec->pending = 1;
+ nvic_irq_update(s);
+ }
}
/* Make pending IRQ active. */
int armv7m_nvic_acknowledge_irq(void *opaque)
{
NVICState *s = (NVICState *)opaque;
- uint32_t irq;
-
- irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
- if (irq == 1023)
- hw_error("Interrupt but no vector\n");
- if (irq >= 32)
- irq -= 16;
- return irq;
+ CPUARMState *env = &s->cpu->env;
+ const int pending = s->vectpending;
+ const int running = nvic_exec_prio(s);
+ int pendgroupprio;
+ VecInfo *vec;
+
+ assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
+
+ vec = &s->vectors[pending];
+
+ assert(vec->enabled);
+ assert(vec->pending);
+
+ pendgroupprio = vec->prio & nvic_gprio_mask(s);
+ assert(pendgroupprio < running);
+
+ trace_nvic_acknowledge_irq(pending, vec->prio);
+
+ vec->active = 1;
+ vec->pending = 0;
+
+ env->v7m.exception = s->vectpending;
+
+ nvic_irq_update(s);
+
+ return env->v7m.exception;
}
void armv7m_nvic_complete_irq(void *opaque, int irq)
{
NVICState *s = (NVICState *)opaque;
- if (irq >= 16)
- irq += 16;
- gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
+ VecInfo *vec;
+
+ assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
+
+ vec = &s->vectors[irq];
+
+ trace_nvic_complete_irq(irq);
+
+ vec->active = 0;
+ if (vec->level) {
+ /* Re-pend the exception if it's still held high; only
+ * happens for extenal IRQs
+ */
+ assert(irq >= NVIC_FIRST_IRQ);
+ vec->pending = 1;
+ }
+
+ nvic_irq_update(s);
+}
+
+/* callback when external interrupt line is changed */
+static void set_irq_level(void *opaque, int n, int level)
+{
+ NVICState *s = opaque;
+ VecInfo *vec;
+
+ n += NVIC_FIRST_IRQ;
+
+ assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
+
+ trace_nvic_set_irq_level(n, level);
+
+ /* The pending status of an external interrupt is
+ * latched on rising edge and exception handler return.
+ *
+ * Pulsing the IRQ will always run the handler
+ * once, and the handler will re-run until the
+ * level is low when the handler completes.
+ */
+ vec = &s->vectors[n];
+ if (level != vec->level) {
+ vec->level = level;
+ if (level) {
+ armv7m_nvic_set_pending(s, n);
+ }
+ }
}
static uint32_t nvic_readl(NVICState *s, uint32_t offset)
{
ARMCPU *cpu = s->cpu;
uint32_t val;
- int irq;
switch (offset) {
case 4: /* Interrupt Control Type. */
- return (s->num_irq / 32) - 1;
+ return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
case 0x10: /* SysTick Control and Status. */
val = s->systick.control;
s->systick.control &= ~SYSTICK_COUNTFLAG;
@@ -195,33 +471,29 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
case 0xd04: /* Interrupt Control State. */
/* VECTACTIVE */
val = cpu->env.v7m.exception;
- if (val == 1023) {
- val = 0;
- } else if (val >= 32) {
- val -= 16;
- }
/* VECTPENDING */
- if (s->gic.current_pending[0] != 1023)
- val |= (s->gic.current_pending[0] << 12);
- /* ISRPENDING and RETTOBASE */
- for (irq = 32; irq < s->num_irq; irq++) {
- if (s->gic.irq_state[irq].pending) {
- val |= (1 << 22);
- break;
- }
- if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active) {
- val |= (1 << 11);
- }
+ val |= (s->vectpending & 0xff) << 12;
+ /* ISRPENDING - set if any external IRQ is pending */
+ if (nvic_isrpending(s)) {
+ val |= (1 << 22);
+ }
+ /* RETTOBASE - set if only one handler is active */
+ if (nvic_rettobase(s)) {
+ val |= (1 << 11);
}
/* PENDSTSET */
- if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
val |= (1 << 26);
+ }
/* PENDSVSET */
- if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
val |= (1 << 28);
+ }
/* NMIPENDSET */
- if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
+ if (s->vectors[ARMV7M_EXCP_NMI].pending) {
val |= (1 << 31);
+ }
+ /* ISRPREEMPT not implemented */
return val;
case 0xd08: /* Vector Table Offset. */
return cpu->env.v7m.vecbase;
@@ -234,20 +506,48 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
return cpu->env.v7m.ccr;
case 0xd24: /* System Handler Status. */
val = 0;
- if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
- if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
- if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
- if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
- if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
- if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
- if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
- if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
- if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
- if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
- if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
- if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
- if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
- if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
+ if (s->vectors[ARMV7M_EXCP_MEM].active) {
+ val |= (1 << 0);
+ }
+ if (s->vectors[ARMV7M_EXCP_BUS].active) {
+ val |= (1 << 1);
+ }
+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {
+ val |= (1 << 3);
+ }
+ if (s->vectors[ARMV7M_EXCP_SVC].active) {
+ val |= (1 << 7);
+ }
+ if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
+ val |= (1 << 8);
+ }
+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
+ val |= (1 << 10);
+ }
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
+ val |= (1 << 11);
+ }
+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
+ val |= (1 << 12);
+ }
+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {
+ val |= (1 << 13);
+ }
+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {
+ val |= (1 << 14);
+ }
+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {
+ val |= (1 << 15);
+ }
+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
+ val |= (1 << 16);
+ }
+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
+ val |= (1 << 17);
+ }
+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
+ val |= (1 << 18);
+ }
return val;
case 0xd28: /* Configurable Fault Status. */
return cpu->env.v7m.cfsr;
@@ -341,14 +641,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
if (value & (1 << 28)) {
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
} else if (value & (1 << 27)) {
- s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
- gic_update(&s->gic);
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
}
if (value & (1 << 26)) {
armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
} else if (value & (1 << 25)) {
- s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
- gic_update(&s->gic);
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
}
break;
case 0xd08: /* Vector Table Offset. */
@@ -366,6 +664,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
}
s->prigroup = extract32(value, 8, 3);
+ nvic_irq_update(s);
}
break;
case 0xd10: /* System Control. */
@@ -386,9 +685,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
case 0xd24: /* System Handler Control. */
/* TODO: Real hardware allows you to set/clear the active bits
under some circumstances. We don't implement this. */
- s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
- s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
- s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
+ nvic_irq_update(s);
break;
case 0xd28: /* Configurable Fault Status. */
cpu->env.v7m.cfsr &= ~value; /* W1C */
@@ -410,13 +710,16 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
"NVIC: Aux fault status registers unimplemented\n");
break;
case 0xf00: /* Software Triggered Interrupt Register */
+ {
/* user mode can only write to STIR if CCR.USERSETMPEND permits it */
- if ((value & 0x1ff) < s->num_irq &&
+ int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
+ if (excnum < s->num_irq &&
(arm_current_el(&cpu->env) ||
(cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
- gic_set_pending_private(&s->gic, 0, value & 0x1ff);
+ armv7m_nvic_set_pending(s, excnum);
}
break;
+ }
default:
qemu_log_mask(LOG_GUEST_ERROR,
"NVIC: Bad write offset 0x%x\n", offset);
@@ -428,28 +731,80 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
{
NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
- int i;
+ unsigned i, startvec, end;
uint32_t val;
switch (offset) {
+ /* reads of set and clear both return the status */
+ case 0x100 ... 0x13f: /* NVIC Set enable */
+ offset += 0x80;
+ /* fall through */
+ case 0x180 ... 0x1bf: /* NVIC Clear enable */
+ val = 0;
+ startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
+
+ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
+ if (s->vectors[startvec + i].enabled) {
+ val |= (1 << i);
+ }
+ }
+ break;
+ case 0x200 ... 0x23f: /* NVIC Set pend */
+ offset += 0x80;
+ /* fall through */
+ case 0x280 ... 0x2bf: /* NVIC Clear pend */
+ val = 0;
+ startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
+ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
+ if (s->vectors[startvec + i].pending) {
+ val |= (1 << i);
+ }
+ }
+ break;
+ case 0x300 ... 0x33f: /* NVIC Active */
+ val = 0;
+ startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
+
+ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
+ if (s->vectors[startvec + i].active) {
+ val |= (1 << i);
+ }
+ }
+ break;
+ case 0x400 ... 0x5ef: /* NVIC Priority */
+ val = 0;
+ startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
+
+ for (i = 0; i < size && startvec + i < s->num_irq; i++) {
+ val |= s->vectors[startvec + i].prio << (8 * i);
+ }
+ break;
case 0xd18 ... 0xd23: /* System Handler Priority. */
val = 0;
for (i = 0; i < size; i++) {
- val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
+ val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
}
- return val;
+ break;
case 0xfe0 ... 0xfff: /* ID. */
if (offset & 3) {
- return 0;
+ val = 0;
+ } else {
+ val = nvic_id[(offset - 0xfe0) >> 2];
+ }
+ break;
+ default:
+ if (size == 4) {
+ val = nvic_readl(s, offset);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "NVIC: Bad read of size %d at offset 0x%x\n",
+ size, offset);
+ val = 0;
}
- return nvic_id[(offset - 0xfe0) >> 2];
- }
- if (size == 4) {
- return nvic_readl(s, offset);
}
- qemu_log_mask(LOG_GUEST_ERROR,
- "NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
- return 0;
+
+ trace_nvic_sysreg_read(addr, val, size);
+ return val;
}
static void nvic_sysreg_write(void *opaque, hwaddr addr,
@@ -457,15 +812,59 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,
{
NVICState *s = (NVICState *)opaque;
uint32_t offset = addr;
- int i;
+ unsigned i, startvec, end;
+ unsigned setval = 0;
+
+ trace_nvic_sysreg_write(addr, value, size);
switch (offset) {
+ case 0x100 ... 0x13f: /* NVIC Set enable */
+ offset += 0x80;
+ setval = 1;
+ /* fall through */
+ case 0x180 ... 0x1bf: /* NVIC Clear enable */
+ startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
+
+ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
+ if (value & (1 << i)) {
+ s->vectors[startvec + i].enabled = setval;
+ }
+ }
+ nvic_irq_update(s);
+ return;
+ case 0x200 ... 0x23f: /* NVIC Set pend */
+ /* the special logic in armv7m_nvic_set_pending()
+ * is not needed since IRQs are never escalated
+ */
+ offset += 0x80;
+ setval = 1;
+ /* fall through */
+ case 0x280 ... 0x2bf: /* NVIC Clear pend */
+ startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
+
+ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
+ if (value & (1 << i)) {
+ s->vectors[startvec + i].pending = setval;
+ }
+ }
+ nvic_irq_update(s);
+ return;
+ case 0x300 ... 0x33f: /* NVIC Active */
+ return; /* R/O */
+ case 0x400 ... 0x5ef: /* NVIC Priority */
+ startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
+
+ for (i = 0; i < size && startvec + i < s->num_irq; i++) {
+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
+ }
+ nvic_irq_update(s);
+ return;
case 0xd18 ... 0xd23: /* System Handler Priority. */
for (i = 0; i < size; i++) {
- s->gic.priority1[(offset - 0xd14) + i][0] =
- (value >> (i * 8)) & 0xff;
+ unsigned hdlidx = (offset - 0xd14) + i;
+ set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
}
- gic_update(&s->gic);
+ nvic_irq_update(s);
return;
}
if (size == 4) {
@@ -482,11 +881,50 @@ static const MemoryRegionOps nvic_sysreg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static int nvic_post_load(void *opaque, int version_id)
+{
+ NVICState *s = opaque;
+ unsigned i;
+
+ /* Check for out of range priority settings */
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
+ s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
+ s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
+ return 1;
+ }
+ for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) {
+ if (s->vectors[i].prio & ~0xff) {
+ return 1;
+ }
+ }
+
+ nvic_recompute_state(s);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_VecInfo = {
+ .name = "armv7m_nvic_info",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_INT16(prio, VecInfo),
+ VMSTATE_UINT8(enabled, VecInfo),
+ VMSTATE_UINT8(pending, VecInfo),
+ VMSTATE_UINT8(active, VecInfo),
+ VMSTATE_UINT8(level, VecInfo),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_nvic = {
.name = "armv7m_nvic",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
+ .post_load = &nvic_post_load,
.fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
+ vmstate_VecInfo, VecInfo),
VMSTATE_UINT32(systick.control, NVICState),
VMSTATE_UINT32(systick.reload, NVICState),
VMSTATE_INT64(systick.tick, NVICState),
@@ -496,48 +934,72 @@ static const VMStateDescription vmstate_nvic = {
}
};
+static Property props_nvic[] = {
+ /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
+ DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void armv7m_nvic_reset(DeviceState *dev)
{
NVICState *s = NVIC(dev);
- NVICClass *nc = NVIC_GET_CLASS(s);
- nc->parent_reset(dev);
- /* Common GIC reset resets to disabled; the NVIC doesn't have
- * per-CPU interfaces so mark our non-existent CPU interface
- * as enabled by default, and with a priority mask which allows
- * all interrupts through.
+
+ s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
+ /* MEM, BUS, and USAGE are enabled through
+ * the System Handler Control register
*/
- s->gic.cpu_ctlr[0] = GICC_CTLR_EN_GRP0;
- s->gic.priority_mask[0] = 0x100;
- /* The NVIC as a whole is always enabled. */
- s->gic.ctlr = 1;
+ s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
+ s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
+ s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
+ s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
+
+ s->vectors[ARMV7M_EXCP_RESET].prio = -3;
+ s->vectors[ARMV7M_EXCP_NMI].prio = -2;
+ s->vectors[ARMV7M_EXCP_HARD].prio = -1;
+
+ /* Strictly speaking the reset handler should be enabled.
+ * However, we don't simulate soft resets through the NVIC,
+ * and the reset vector should never be pended.
+ * So we leave it disabled to catch logic errors.
+ */
+
+ s->exception_prio = NVIC_NOEXC_PRIO;
+ s->vectpending = 0;
+
systick_reset(s);
}
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
{
NVICState *s = NVIC(dev);
- NVICClass *nc = NVIC_GET_CLASS(s);
- Error *local_err = NULL;
s->cpu = ARM_CPU(qemu_get_cpu(0));
assert(s->cpu);
- /* The NVIC always has only one CPU */
- s->gic.num_cpu = 1;
- /* Tell the common code we're an NVIC */
- s->gic.revision = 0xffffffff;
- s->num_irq = s->gic.num_irq;
- nc->parent_realize(dev, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+
+ if (s->num_irq > NVIC_MAX_IRQ) {
+ error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq);
return;
}
- gic_init_irqs_and_distributor(&s->gic);
- /* The NVIC and system controller register area looks like this:
- * 0..0xff : system control registers, including systick
- * 0x100..0xcff : GIC-like registers
- * 0xd00..0xfff : system control registers
- * We use overlaying to put the GIC like registers
- * over the top of the system control register region.
+
+ qdev_init_gpio_in(dev, set_irq_level, s->num_irq);
+
+ /* include space for internal exception vectors */
+ s->num_irq += NVIC_FIRST_IRQ;
+
+ /* The NVIC and System Control Space (SCS) starts at 0xe000e000
+ * and looks like this:
+ * 0x004 - ICTR
+ * 0x010 - 0x1c - systick
+ * 0x100..0x7ec - NVIC
+ * 0x7f0..0xcff - Reserved
+ * 0xd00..0xd3c - SCS registers
+ * 0xd40..0xeff - Reserved or Not implemented
+ * 0xf00 - STIR
+ *
+ * At the moment there is only one thing in the container region,
+ * but we leave it in place to allow us to pull systick out into
+ * its own device object later.
*/
memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
/* The system register region goes at the bottom of the priority
@@ -546,14 +1008,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
"nvic_sysregs", 0x1000);
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
- /* Alias the GIC region so we can get only the section of it
- * we need, and layer it on top of the system register region.
- */
- memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s),
- "nvic-gic", &s->gic.iomem,
- 0x100, 0xc00);
- memory_region_add_subregion_overlap(&s->container, 0x100,
- &s->gic_iomem_alias, 1);
+
/* Map the whole thing into system memory at the location required
* by the v7M architecture.
*/
@@ -569,36 +1024,31 @@ static void armv7m_nvic_instance_init(Object *obj)
* any user-specified property setting, so just modify the
* value in the GICState struct.
*/
- GICState *s = ARM_GIC_COMMON(obj);
DeviceState *dev = DEVICE(obj);
NVICState *nvic = NVIC(obj);
- /* The ARM v7m may have anything from 0 to 496 external interrupt
- * IRQ lines. We default to 64. Other boards may differ and should
- * set the num-irq property appropriately.
- */
- s->num_irq = 64;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ sysbus_init_irq(sbd, &nvic->excpout);
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
}
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
{
- NVICClass *nc = NVIC_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- nc->parent_reset = dc->reset;
- nc->parent_realize = dc->realize;
dc->vmsd = &vmstate_nvic;
+ dc->props = props_nvic;
dc->reset = armv7m_nvic_reset;
dc->realize = armv7m_nvic_realize;
}
static const TypeInfo armv7m_nvic_info = {
.name = TYPE_NVIC,
- .parent = TYPE_ARM_GIC_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
.instance_init = armv7m_nvic_instance_init,
.instance_size = sizeof(NVICState),
.class_init = armv7m_nvic_class_init,
- .class_size = sizeof(NVICClass),
+ .class_size = sizeof(SysBusDeviceClass),
};
static void armv7m_nvic_register_types(void)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 39a538d..729c128 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -161,3 +161,18 @@ gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size,
gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 redistributor %x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error"
gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor %x interrupt %d level changed to %d"
gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor %x pending SGI %d"
+
+# hw/intc/armv7m_nvic.c
+nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
+nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
+nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
+nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
+nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
+nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
+nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
+nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
+nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
+nvic_complete_irq(int irq) "NVIC complete IRQ %d"
+nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
+nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC Peter Maydell
` (16 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
The M profile condition for when we can take a pending exception or
interrupt is not the same as that for A/R profile. The code
originally copied from the A/R profile version of the
cpu_exec_interrupt function only worked by chance for the
very simple case of exceptions being masked by PRIMASK.
Replace it with a call to a function in the NVIC code that
correctly compares the priority of the pending exception
against the current execution priority of the CPU.
[Michael Davidsaver's patchset had a patch to do something
similar but the implementation ended up being a rewrite.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 8 ++++++++
hw/intc/armv7m_nvic.c | 7 +++++++
target/arm/cpu.c | 16 ++++++++--------
3 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 38a8e00..649f237 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1356,6 +1356,14 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure);
/* Interface between CPU and Interrupt controller. */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(void *opaque);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ return true;
+}
+#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index fb4c985..6a03e2c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -286,6 +286,13 @@ static inline int nvic_exec_prio(NVICState *s)
return MIN(running, s->exception_prio);
}
+bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ NVICState *s = opaque;
+
+ return nvic_exec_prio(s) > nvic_pending_prio(s);
+}
+
/* caller must call nvic_irq_update() after this */
static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
{
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f7157dc..04b062c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -338,13 +338,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUARMState *env = &cpu->env;
bool ret = false;
-
- if (interrupt_request & CPU_INTERRUPT_FIQ
- && !(env->daif & PSTATE_F)) {
- cs->exception_index = EXCP_FIQ;
- cc->do_interrupt(cs);
- ret = true;
- }
/* ARMv7-M interrupt return works by loading a magic value
* into the PC. On real hardware the load causes the
* return to occur. The qemu implementation performs the
@@ -354,9 +347,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
* the stack if an interrupt occurred at the wrong time.
* We avoid this by disabling interrupts when
* pc contains a magic address.
+ *
+ * ARMv7-M interrupt masking works differently than -A or -R.
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
+ * masking FIQ and IRQ interrupts, an exception is taken only
+ * if it is higher priority than the current execution priority
+ * (which depends on state like BASEPRI, FAULTMASK and the
+ * currently active exception).
*/
if (interrupt_request & CPU_INTERRUPT_HARD
- && !(env->daif & PSTATE_I)
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))
&& (env->regs[15] < 0xfffffff0)) {
cs->exception_index = EXCP_IRQ;
cc->do_interrupt(cs);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary Peter Maydell
` (15 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Michael Davidsaver <mdavidsaver@gmail.com>
Now that the NVIC is its own separate implementation, we can
clean up the GIC code by removing REV_NVIC and conditionals
which use it.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/gic_internal.h | 7 ++-----
hw/intc/arm_gic.c | 31 +++++--------------------------
hw/intc/arm_gic_common.c | 23 ++++++++---------------
3 files changed, 15 insertions(+), 46 deletions(-)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 3f31174..7fe87b1 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -25,9 +25,7 @@
#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
-/* The NVIC has 16 internal vectors. However these are not exposed
- through the normal GIC interface. */
-#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
+#define GIC_BASE_IRQ 0
#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
@@ -75,7 +73,6 @@
/* The special cases for the revision property: */
#define REV_11MPCORE 0
-#define REV_NVIC 0xffffffff
void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
@@ -87,7 +84,7 @@ void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
static inline bool gic_test_pending(GICState *s, int irq, int cm)
{
- if (s->revision == REV_NVIC || s->revision == REV_11MPCORE) {
+ if (s->revision == REV_11MPCORE) {
return s->irq_state[irq].pending & cm;
} else {
/* Edge-triggered interrupts are marked pending on a rising edge, but
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 521aac3..8e5a9d8 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -156,17 +156,6 @@ static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
}
}
-static void gic_set_irq_nvic(GICState *s, int irq, int level,
- int cm, int target)
-{
- if (level) {
- GIC_SET_LEVEL(irq, cm);
- GIC_SET_PENDING(irq, target);
- } else {
- GIC_CLEAR_LEVEL(irq, cm);
- }
-}
-
static void gic_set_irq_generic(GICState *s, int irq, int level,
int cm, int target)
{
@@ -214,8 +203,6 @@ static void gic_set_irq(void *opaque, int irq, int level)
if (s->revision == REV_11MPCORE) {
gic_set_irq_11mpcore(s, irq, level, cm, target);
- } else if (s->revision == REV_NVIC) {
- gic_set_irq_nvic(s, irq, level, cm, target);
} else {
gic_set_irq_generic(s, irq, level, cm, target);
}
@@ -367,7 +354,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return 1023;
}
- if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
+ if (s->revision == REV_11MPCORE) {
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
@@ -589,11 +576,6 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
DPRINTF("Set %d pending mask %x\n", irq, cm);
GIC_SET_PENDING(irq, cm);
}
- } else if (s->revision == REV_NVIC) {
- if (GIC_TEST_LEVEL(irq, cm)) {
- DPRINTF("Set nvic %d pending mask %x\n", irq, cm);
- GIC_SET_PENDING(irq, cm);
- }
}
group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
@@ -768,7 +750,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
} else if (offset < 0xf10) {
goto bad_reg;
} else if (offset < 0xf30) {
- if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
+ if (s->revision == REV_11MPCORE) {
goto bad_reg;
}
@@ -802,9 +784,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
case 2:
res = gic_id_gicv2[(offset - 0xfd0) >> 2];
break;
- case REV_NVIC:
- /* Shouldn't be able to get here */
- abort();
default:
res = 0;
}
@@ -1028,7 +1007,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
+ if (s->revision == REV_11MPCORE) {
if (value & (1 << (i * 2))) {
GIC_SET_MODEL(irq + i);
} else {
@@ -1046,7 +1025,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
goto bad_reg;
} else if (offset < 0xf20) {
/* GICD_CPENDSGIRn */
- if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
+ if (s->revision == REV_11MPCORE) {
goto bad_reg;
}
irq = (offset - 0xf10);
@@ -1060,7 +1039,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
}
} else if (offset < 0xf30) {
/* GICD_SPENDSGIRn */
- if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
+ if (s->revision == REV_11MPCORE) {
goto bad_reg;
}
irq = (offset - 0xf20);
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 4a8df44..70f1134 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -99,9 +99,7 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
* [N+32..N+63] PPIs for CPU 1
* ...
*/
- if (s->revision != REV_NVIC) {
- i += (GIC_INTERNAL * s->num_cpu);
- }
+ i += (GIC_INTERNAL * s->num_cpu);
qdev_init_gpio_in(DEVICE(s), handler, i);
for (i = 0; i < s->num_cpu; i++) {
@@ -121,16 +119,12 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
- if (s->revision != REV_NVIC) {
- /* This is the main CPU interface "for this core". It is always
- * present because it is required by both software emulation and KVM.
- * NVIC is not handled here because its CPU interface is different,
- * neither it can use KVM.
- */
- memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
- s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
- sysbus_init_mmio(sbd, &s->cpuiomem[0]);
- }
+ /* This is the main CPU interface "for this core". It is always
+ * present because it is required by both software emulation and KVM.
+ */
+ memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
+ s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
+ sysbus_init_mmio(sbd, &s->cpuiomem[0]);
}
static void arm_gic_common_realize(DeviceState *dev, Error **errp)
@@ -162,7 +156,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
}
if (s->security_extn &&
- (s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
+ (s->revision == REV_11MPCORE)) {
error_setg(errp, "this GIC revision does not implement "
"the security extensions");
return;
@@ -255,7 +249,6 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
/* Revision can be 1 or 2 for GIC architecture specification
* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
- * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
*/
DEFINE_PROP_UINT32("revision", GICState, revision, 1),
/* True if the GIC should implement the security extensions */
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 18/30] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value Peter Maydell
` (14 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Michael Davidsaver <mdavidsaver@gmail.com>
The v7M exception architecture requires that if a synchronous
exception cannot be taken immediately (because it is disabled
or at too low a priority) then it should be escalated to
HardFault (and the HardFault exception is then taken).
Implement this escalation logic.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
[PMM: extracted from another patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++
target/arm/helper.c | 2 --
2 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6a03e2c..479acfc 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -352,6 +352,59 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
vec = &s->vectors[irq];
trace_nvic_set_pending(irq, vec->enabled, vec->prio);
+
+
+ if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
+ /* If a synchronous exception is pending then it may be
+ * escalated to HardFault if:
+ * * it is equal or lower priority to current execution
+ * * it is disabled
+ * (ie we need to take it immediately but we can't do so).
+ * Asynchronous exceptions (and interrupts) simply remain pending.
+ *
+ * For QEMU, we don't have any imprecise (asynchronous) faults,
+ * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
+ * synchronous.
+ * Debug exceptions are awkward because only Debug exceptions
+ * resulting from the BKPT instruction should be escalated,
+ * but we don't currently implement any Debug exceptions other
+ * than those that result from BKPT, so we treat all debug exceptions
+ * as needing escalation.
+ *
+ * This all means we can identify whether to escalate based only on
+ * the exception number and don't (yet) need the caller to explicitly
+ * tell us whether this exception is synchronous or not.
+ */
+ int running = nvic_exec_prio(s);
+ bool escalate = false;
+
+ if (vec->prio >= running) {
+ trace_nvic_escalate_prio(irq, vec->prio, running);
+ escalate = true;
+ } else if (!vec->enabled) {
+ trace_nvic_escalate_disabled(irq);
+ escalate = true;
+ }
+
+ if (escalate) {
+ if (running < 0) {
+ /* We want to escalate to HardFault but we can't take a
+ * synchronous HardFault at this point either. This is a
+ * Lockup condition due to a guest bug. We don't model
+ * Lockup, so report via cpu_abort() instead.
+ */
+ cpu_abort(&s->cpu->parent_obj,
+ "Lockup: can't escalate %d to HardFault "
+ "(current priority %d)\n", irq, running);
+ }
+
+ /* We can do the escalation, so we take HardFault instead */
+ irq = ARMV7M_EXCP_HARD;
+ vec = &s->vectors[irq];
+ s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
+ }
+ }
+
if (!vec->pending) {
vec->pending = 1;
nvic_irq_update(s);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bcedb4a..2fc6802 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6106,8 +6106,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
/* For exceptions we just mark as pending on the NVIC, and let that
handle it. */
- /* TODO: Need to escalate if the current priority is higher than the
- one we're raising. */
switch (cs->exception_index) {
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 18/30] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start Peter Maydell
` (13 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Having armv7m_nvic_acknowledge_irq() return the new value of
env->v7m.exception and its one caller assign the return value
back to env->v7m.exception is pointless. Just make the return
type void instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 2 +-
hw/intc/armv7m_nvic.c | 4 +---
target/arm/helper.c | 2 +-
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 649f237..68ad00c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1365,7 +1365,7 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
}
#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
-int armv7m_nvic_acknowledge_irq(void *opaque);
+void armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);
/* Interface for defining coprocessor registers.
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 479acfc..9336bca 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -412,7 +412,7 @@ void armv7m_nvic_set_pending(void *opaque, int irq)
}
/* Make pending IRQ active. */
-int armv7m_nvic_acknowledge_irq(void *opaque)
+void armv7m_nvic_acknowledge_irq(void *opaque)
{
NVICState *s = (NVICState *)opaque;
CPUARMState *env = &s->cpu->env;
@@ -439,8 +439,6 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
env->v7m.exception = s->vectpending;
nvic_irq_update(s);
-
- return env->v7m.exception;
}
void armv7m_nvic_complete_irq(void *opaque, int irq)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2fc6802..85d1364 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6142,7 +6142,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
return;
case EXCP_IRQ:
- env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
+ armv7m_nvic_acknowledge_irq(env->nvic);
break;
case EXCP_EXCEPTION_EXIT:
do_v7m_exception_exit(env);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 18/30] armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE Peter Maydell
` (12 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Michael Davidsaver <mdavidsaver@gmail.com>
All the places in armv7m_cpu_do_interrupt() which pend an
exception in the NVIC are doing so for synchronous
exceptions. We know that we will always take some
exception in this case, so we can just acknowledge it
immediately, rather than returning and then immediately
being called again because the NVIC has raised its outbound
IRQ line.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
[PMM: tweaked commit message; added DEBUG to the set of
exceptions we handle immediately, since it is synchronous
when it results from the BKPT instruction]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 85d1364..664f030 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6110,22 +6110,22 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
- return;
+ break;
case EXCP_NOCP:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
- return;
+ break;
case EXCP_SWI:
/* The PC already points to the next instruction. */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
- return;
+ break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
/* TODO: if we implemented the MPU registers, this is where we
* should set the MMFAR, etc from exception.fsr and exception.vaddress.
*/
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
- return;
+ break;
case EXCP_BKPT:
if (semihosting_enabled()) {
int nr;
@@ -6140,9 +6140,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
}
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
- return;
+ break;
case EXCP_IRQ:
- armv7m_nvic_acknowledge_irq(env->nvic);
break;
case EXCP_EXCEPTION_EXIT:
do_v7m_exception_exit(env);
@@ -6152,6 +6151,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
+ armv7m_nvic_acknowledge_irq(env->nvic);
+
+ qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
+
/* Align stack pointer if the guest wants that */
if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
env->regs[13] -= 4;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 19/30] armv7m: Simpler and faster exception start Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions Peter Maydell
` (11 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Michael Davidsaver <mdavidsaver@gmail.com>
The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both
documented as UNPREDICTABLE if you write a 1 to them when
the processor is not halted in Debug state (ie stopped
and under the control of an external JTAG debugger).
Since we don't implement Debug state or emulated JTAG
these bits are always UNPREDICTABLE for us. Instead of
logging them as unimplemented we can simply log writes
as guest errors and ignore them.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
[PMM: change extracted from another patch; commit message
constructed from scratch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 9336bca..456480a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -716,10 +716,14 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
qemu_irq_pulse(s->sysresetreq);
}
if (value & 2) {
- qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Setting VECTCLRACTIVE when not in DEBUG mode "
+ "is UNPREDICTABLE\n");
}
if (value & 1) {
- qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Setting VECTRESET when not in DEBUG mode "
+ "is UNPREDICTABLE\n");
}
s->prigroup = extract32(value, 8, 3);
nvic_irq_update(s);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 20/30] armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency Peter Maydell
` (10 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Extract the code from the tail end of arm_v7m_do_interrupt() which
enters the exception handler into a pair of utility functions
v7m_exception_taken() and v7m_push_stack(), which correspond roughly
to the pseudocode PushStack() and ExceptionTaken().
This also requires us to move the arm_v7m_load_vector() utility
routine up so we can call it.
Handling illegal exception returns has some cases where we want to
take a UsageFault either on an existing stack frame or with a new
stack frame but with a specific LR value, so we want to be able to
call these without having to go via arm_v7m_cpu_do_interrupt().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper.c | 118 ++++++++++++++++++++++++++++++----------------------
1 file changed, 68 insertions(+), 50 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 664f030..be731dc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6002,6 +6002,72 @@ static void switch_v7m_sp(CPUARMState *env, bool new_spsel)
}
}
+static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
+{
+ CPUState *cs = CPU(cpu);
+ CPUARMState *env = &cpu->env;
+ MemTxResult result;
+ hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4;
+ uint32_t addr;
+
+ addr = address_space_ldl(cs->as, vec,
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
+ * which would then be immediately followed by our failing to load
+ * the entry vector for that HardFault, which is a Lockup case.
+ * Since we don't model Lockup, we just report this guest error
+ * via cpu_abort().
+ */
+ cpu_abort(cs, "Failed to read from exception vector table "
+ "entry %08x\n", (unsigned)vec);
+ }
+ return addr;
+}
+
+static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
+{
+ /* Do the "take the exception" parts of exception entry,
+ * but not the pushing of state to the stack. This is
+ * similar to the pseudocode ExceptionTaken() function.
+ */
+ CPUARMState *env = &cpu->env;
+ uint32_t addr;
+
+ armv7m_nvic_acknowledge_irq(env->nvic);
+ switch_v7m_sp(env, 0);
+ /* Clear IT bits */
+ env->condexec_bits = 0;
+ env->regs[14] = lr;
+ addr = arm_v7m_load_vector(cpu);
+ env->regs[15] = addr & 0xfffffffe;
+ env->thumb = addr & 1;
+}
+
+static void v7m_push_stack(ARMCPU *cpu)
+{
+ /* Do the "set up stack frame" part of exception entry,
+ * similar to pseudocode PushStack().
+ */
+ CPUARMState *env = &cpu->env;
+ uint32_t xpsr = xpsr_read(env);
+
+ /* Align stack pointer if the guest wants that */
+ if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
+ env->regs[13] -= 4;
+ xpsr |= 0x200;
+ }
+ /* Switch to the handler mode. */
+ v7m_push(env, xpsr);
+ v7m_push(env, env->regs[15]);
+ v7m_push(env, env->regs[14]);
+ v7m_push(env, env->regs[12]);
+ v7m_push(env, env->regs[3]);
+ v7m_push(env, env->regs[2]);
+ v7m_push(env, env->regs[1]);
+ v7m_push(env, env->regs[0]);
+}
+
static void do_v7m_exception_exit(CPUARMState *env)
{
uint32_t type;
@@ -6063,37 +6129,11 @@ static void arm_log_exception(int idx)
}
}
-static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
-
-{
- CPUState *cs = CPU(cpu);
- CPUARMState *env = &cpu->env;
- MemTxResult result;
- hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4;
- uint32_t addr;
-
- addr = address_space_ldl(cs->as, vec,
- MEMTXATTRS_UNSPECIFIED, &result);
- if (result != MEMTX_OK) {
- /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
- * which would then be immediately followed by our failing to load
- * the entry vector for that HardFault, which is a Lockup case.
- * Since we don't model Lockup, we just report this guest error
- * via cpu_abort().
- */
- cpu_abort(cs, "Failed to read from exception vector table "
- "entry %08x\n", (unsigned)vec);
- }
- return addr;
-}
-
void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
- uint32_t xpsr = xpsr_read(env);
uint32_t lr;
- uint32_t addr;
arm_log_exception(cs->exception_index);
@@ -6151,31 +6191,9 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
- armv7m_nvic_acknowledge_irq(env->nvic);
-
+ v7m_push_stack(cpu);
+ v7m_exception_taken(cpu, lr);
qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
-
- /* Align stack pointer if the guest wants that */
- if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
- env->regs[13] -= 4;
- xpsr |= 0x200;
- }
- /* Switch to the handler mode. */
- v7m_push(env, xpsr);
- v7m_push(env, env->regs[15]);
- v7m_push(env, env->regs[14]);
- v7m_push(env, env->regs[12]);
- v7m_push(env, env->regs[3]);
- v7m_push(env, env->regs[2]);
- v7m_push(env, env->regs[1]);
- v7m_push(env, env->regs[0]);
- switch_v7m_sp(env, 0);
- /* Clear IT bits */
- env->condexec_bits = 0;
- env->regs[14] = lr;
- addr = arm_v7m_load_vector(cpu);
- env->regs[15] = addr & 0xfffffffe;
- env->thumb = addr & 1;
}
/* Function used to synchronize QEMU's AArch64 register set with AArch32
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code Peter Maydell
` (9 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Implement the exception return consistency checks
described in the v7M pseudocode ExceptionReturn().
Inspired by a patch from Michael Davidsaver's series, but
this is a reimplementation from scratch based on the
ARM ARM pseudocode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 12 +++++-
hw/intc/armv7m_nvic.c | 12 +++++-
target/arm/helper.c | 112 +++++++++++++++++++++++++++++++++++++++++++++-----
3 files changed, 123 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 68ad00c..045830a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1366,7 +1366,17 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
#endif
void armv7m_nvic_set_pending(void *opaque, int irq);
void armv7m_nvic_acknowledge_irq(void *opaque);
-void armv7m_nvic_complete_irq(void *opaque, int irq);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @opaque: the NVIC
+ * @irq: the exception number to complete
+ *
+ * Returns: -1 if the irq was not active
+ * 1 if completing this irq brought us back to base (no active irqs)
+ * 0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(void *opaque, int irq);
/* Interface for defining coprocessor registers.
* Registers are defined in tables of arm_cp_reginfo structs
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 456480a..718b1a1 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -441,10 +441,11 @@ void armv7m_nvic_acknowledge_irq(void *opaque)
nvic_irq_update(s);
}
-void armv7m_nvic_complete_irq(void *opaque, int irq)
+int armv7m_nvic_complete_irq(void *opaque, int irq)
{
NVICState *s = (NVICState *)opaque;
VecInfo *vec;
+ int ret;
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -452,6 +453,13 @@ void armv7m_nvic_complete_irq(void *opaque, int irq)
trace_nvic_complete_irq(irq);
+ if (!vec->active) {
+ /* Tell the caller this was an illegal exception return */
+ return -1;
+ }
+
+ ret = nvic_rettobase(s);
+
vec->active = 0;
if (vec->level) {
/* Re-pend the exception if it's still held high; only
@@ -462,6 +470,8 @@ void armv7m_nvic_complete_irq(void *opaque, int irq)
}
nvic_irq_update(s);
+
+ return ret;
}
/* callback when external interrupt line is changed */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index be731dc..9081771 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6068,22 +6068,99 @@ static void v7m_push_stack(ARMCPU *cpu)
v7m_push(env, env->regs[0]);
}
-static void do_v7m_exception_exit(CPUARMState *env)
+static void do_v7m_exception_exit(ARMCPU *cpu)
{
+ CPUARMState *env = &cpu->env;
uint32_t type;
uint32_t xpsr;
-
+ bool ufault = false;
+ bool return_to_sp_process = false;
+ bool return_to_handler = false;
+ bool rettobase = false;
+
+ /* We can only get here from an EXCP_EXCEPTION_EXIT, and
+ * arm_v7m_do_unassigned_access() enforces the architectural rule
+ * that jumps to magic addresses don't have magic behaviour unless
+ * we're in Handler mode (compare pseudocode BXWritePC()).
+ */
+ assert(env->v7m.exception != 0);
+
+ /* In the spec pseudocode ExceptionReturn() is called directly
+ * from BXWritePC() and gets the full target PC value including
+ * bit zero. In QEMU's implementation we treat it as a normal
+ * jump-to-register (which is then caught later on), and so split
+ * the target value up between env->regs[15] and env->thumb in
+ * gen_bx(). Reconstitute it.
+ */
type = env->regs[15];
+ if (env->thumb) {
+ type |= 1;
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32
+ " previous exception %d\n",
+ type, env->v7m.exception);
+
+ if (extract32(type, 5, 23) != extract32(-1, 5, 23)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
+ "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
+ }
+
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
/* Auto-clear FAULTMASK on return from other than NMI */
env->daif &= ~PSTATE_F;
}
- if (env->v7m.exception != 0) {
- armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
+
+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
+ case -1:
+ /* attempt to exit an exception that isn't active */
+ ufault = true;
+ break;
+ case 0:
+ /* still an irq active now */
+ break;
+ case 1:
+ /* we returned to base exception level, no nesting.
+ * (In the pseudocode this is written using "NestedActivation != 1"
+ * where we have 'rettobase == false'.)
+ */
+ rettobase = true;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ switch (type & 0xf) {
+ case 1: /* Return to Handler */
+ return_to_handler = true;
+ break;
+ case 13: /* Return to Thread using Process stack */
+ return_to_sp_process = true;
+ /* fall through */
+ case 9: /* Return to Thread using Main stack */
+ if (!rettobase &&
+ !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) {
+ ufault = true;
+ }
+ break;
+ default:
+ ufault = true;
+ }
+
+ if (ufault) {
+ /* Bad exception return: instead of popping the exception
+ * stack, directly take a usage fault on the current stack.
+ */
+ env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+ v7m_exception_taken(cpu, type | 0xf0000000);
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
+ "stackframe: failed exception return integrity check\n");
+ return;
}
/* Switch to the target stack. */
- switch_v7m_sp(env, (type & 4) != 0);
+ switch_v7m_sp(env, return_to_sp_process);
/* Pop registers. */
env->regs[0] = v7m_pop(env);
env->regs[1] = v7m_pop(env);
@@ -6107,11 +6184,24 @@ static void do_v7m_exception_exit(CPUARMState *env)
/* Undo stack alignment. */
if (xpsr & 0x200)
env->regs[13] |= 4;
- /* ??? The exception return type specifies Thread/Handler mode. However
- this is also implied by the xPSR value. Not sure what to do
- if there is a mismatch. */
- /* ??? Likewise for mismatches between the CONTROL register and the stack
- pointer. */
+
+ /* The restored xPSR exception field will be zero if we're
+ * resuming in Thread mode. If that doesn't match what the
+ * exception return type specified then this is a UsageFault.
+ */
+ if (return_to_handler == (env->v7m.exception == 0)) {
+ /* Take an INVPC UsageFault by pushing the stack again. */
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+ env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;
+ v7m_push_stack(cpu);
+ v7m_exception_taken(cpu, type | 0xf0000000);
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
+ "failed exception return integrity check\n");
+ return;
+ }
+
+ /* Otherwise, we have a successful exception exit. */
+ qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
}
static void arm_log_exception(int idx)
@@ -6184,7 +6274,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
case EXCP_IRQ:
break;
case EXCP_EXCEPTION_EXIT:
- do_v7m_exception_exit(env);
+ do_v7m_exception_exit(cpu);
return;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits Peter Maydell
` (8 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set. We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 1 +
linux-user/main.c | 1 +
target/arm/helper.c | 4 ++++
target/arm/translate.c | 8 ++++++--
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 045830a..9e7b2df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -57,6 +57,7 @@
#define EXCP_VFIQ 15
#define EXCP_SEMIHOST 16 /* semihosting call */
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
+#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
diff --git a/linux-user/main.c b/linux-user/main.c
index 9645122..10a3bb3 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -574,6 +574,7 @@ void cpu_loop(CPUARMState *env)
switch(trapnr) {
case EXCP_UDEF:
case EXCP_NOCP:
+ case EXCP_INVSTATE:
{
TaskState *ts = cs->opaque;
uint32_t opcode;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9081771..3f4211b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6245,6 +6245,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
break;
+ case EXCP_INVSTATE:
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+ env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK;
+ break;
case EXCP_SWI:
/* The PC already points to the next instruction. */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index abc1f77..b859f10 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7990,9 +7990,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
TCGv_i32 addr;
TCGv_i64 tmp64;
- /* M variants do not implement ARM mode. */
+ /* M variants do not implement ARM mode; this must raise the INVSTATE
+ * UsageFault exception.
+ */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
+ gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
+ default_exception_el(s));
+ return;
}
cond = insn >> 28;
if (cond == 0xf){
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller Peter Maydell
` (7 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/intc/armv7m_nvic.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 718b1a1..76097b4 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -755,8 +755,17 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
cpu->env.v7m.ccr = value;
break;
case 0xd24: /* System Handler Control. */
- /* TODO: Real hardware allows you to set/clear the active bits
- under some circumstances. We don't implement this. */
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+ s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function Peter Maydell
` (6 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Clement Deschamps <clement.deschamps@antfield.fr>
This adds the BCM2835 SDHost controller from Arasan.
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
Message-id: 20170224164021.9066-2-clement.deschamps@antfield.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/Makefile.objs | 1 +
include/hw/sd/bcm2835_sdhost.h | 48 +++++
hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 478 insertions(+)
create mode 100644 include/hw/sd/bcm2835_sdhost.h
create mode 100644 hw/sd/bcm2835_sdhost.c
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index 31c8330..c2b7664 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -6,3 +6,4 @@ common-obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o
obj-$(CONFIG_OMAP) += omap_mmc.o
obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o
+obj-$(CONFIG_RASPI) += bcm2835_sdhost.o
diff --git a/include/hw/sd/bcm2835_sdhost.h b/include/hw/sd/bcm2835_sdhost.h
new file mode 100644
index 0000000..7520dd6
--- /dev/null
+++ b/include/hw/sd/bcm2835_sdhost.h
@@ -0,0 +1,48 @@
+/*
+ * Raspberry Pi (BCM2835) SD Host Controller
+ *
+ * Copyright (c) 2017 Antfield SAS
+ *
+ * Authors:
+ * Clement Deschamps <clement.deschamps@antfield.fr>
+ * Luc Michel <luc.michel@antfield.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_SDHOST_H
+#define BCM2835_SDHOST_H
+
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+
+#define TYPE_BCM2835_SDHOST "bcm2835-sdhost"
+#define BCM2835_SDHOST(obj) \
+ OBJECT_CHECK(BCM2835SDHostState, (obj), TYPE_BCM2835_SDHOST)
+
+#define BCM2835_SDHOST_FIFO_LEN 16
+
+typedef struct {
+ SysBusDevice busdev;
+ SDBus sdbus;
+ MemoryRegion iomem;
+
+ uint32_t cmd;
+ uint32_t cmdarg;
+ uint32_t status;
+ uint32_t rsp[4];
+ uint32_t config;
+ uint32_t edm;
+ uint32_t vdd;
+ uint32_t hbct;
+ uint32_t hblc;
+ int32_t fifo_pos;
+ int32_t fifo_len;
+ uint32_t fifo[BCM2835_SDHOST_FIFO_LEN];
+ uint32_t datacnt;
+
+ qemu_irq irq;
+} BCM2835SDHostState;
+
+#endif
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
new file mode 100644
index 0000000..f7f4e65
--- /dev/null
+++ b/hw/sd/bcm2835_sdhost.c
@@ -0,0 +1,429 @@
+/*
+ * Raspberry Pi (BCM2835) SD Host Controller
+ *
+ * Copyright (c) 2017 Antfield SAS
+ *
+ * Authors:
+ * Clement Deschamps <clement.deschamps@antfield.fr>
+ * Luc Michel <luc.michel@antfield.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "sysemu/blockdev.h"
+#include "hw/sd/bcm2835_sdhost.h"
+
+#define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
+#define BCM2835_SDHOST_BUS(obj) \
+ OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS)
+
+#define SDCMD 0x00 /* Command to SD card - 16 R/W */
+#define SDARG 0x04 /* Argument to SD card - 32 R/W */
+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
+#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
+#define SDRSP0 0x10 /* SD card rsp (31:0) - 32 R */
+#define SDRSP1 0x14 /* SD card rsp (63:32) - 32 R */
+#define SDRSP2 0x18 /* SD card rsp (95:64) - 32 R */
+#define SDRSP3 0x1c /* SD card rsp (127:96) - 32 R */
+#define SDHSTS 0x20 /* SD host status - 11 R */
+#define SDVDD 0x30 /* SD card power control - 1 R/W */
+#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
+#define SDHCFG 0x38 /* Host configuration - 2 R/W */
+#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
+#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
+
+#define SDCMD_NEW_FLAG 0x8000
+#define SDCMD_FAIL_FLAG 0x4000
+#define SDCMD_BUSYWAIT 0x800
+#define SDCMD_NO_RESPONSE 0x400
+#define SDCMD_LONG_RESPONSE 0x200
+#define SDCMD_WRITE_CMD 0x80
+#define SDCMD_READ_CMD 0x40
+#define SDCMD_CMD_MASK 0x3f
+
+#define SDCDIV_MAX_CDIV 0x7ff
+
+#define SDHSTS_BUSY_IRPT 0x400
+#define SDHSTS_BLOCK_IRPT 0x200
+#define SDHSTS_SDIO_IRPT 0x100
+#define SDHSTS_REW_TIME_OUT 0x80
+#define SDHSTS_CMD_TIME_OUT 0x40
+#define SDHSTS_CRC16_ERROR 0x20
+#define SDHSTS_CRC7_ERROR 0x10
+#define SDHSTS_FIFO_ERROR 0x08
+/* Reserved */
+/* Reserved */
+#define SDHSTS_DATA_FLAG 0x01
+
+#define SDHCFG_BUSY_IRPT_EN (1 << 10)
+#define SDHCFG_BLOCK_IRPT_EN (1 << 8)
+#define SDHCFG_SDIO_IRPT_EN (1 << 5)
+#define SDHCFG_DATA_IRPT_EN (1 << 4)
+#define SDHCFG_SLOW_CARD (1 << 3)
+#define SDHCFG_WIDE_EXT_BUS (1 << 2)
+#define SDHCFG_WIDE_INT_BUS (1 << 1)
+#define SDHCFG_REL_CMD_LINE (1 << 0)
+
+#define SDEDM_FORCE_DATA_MODE (1 << 19)
+#define SDEDM_CLOCK_PULSE (1 << 20)
+#define SDEDM_BYPASS (1 << 21)
+
+#define SDEDM_WRITE_THRESHOLD_SHIFT 9
+#define SDEDM_READ_THRESHOLD_SHIFT 14
+#define SDEDM_THRESHOLD_MASK 0x1f
+
+#define SDEDM_FSM_MASK 0xf
+#define SDEDM_FSM_IDENTMODE 0x0
+#define SDEDM_FSM_DATAMODE 0x1
+#define SDEDM_FSM_READDATA 0x2
+#define SDEDM_FSM_WRITEDATA 0x3
+#define SDEDM_FSM_READWAIT 0x4
+#define SDEDM_FSM_READCRC 0x5
+#define SDEDM_FSM_WRITECRC 0x6
+#define SDEDM_FSM_WRITEWAIT1 0x7
+#define SDEDM_FSM_POWERDOWN 0x8
+#define SDEDM_FSM_POWERUP 0x9
+#define SDEDM_FSM_WRITESTART1 0xa
+#define SDEDM_FSM_WRITESTART2 0xb
+#define SDEDM_FSM_GENPULSES 0xc
+#define SDEDM_FSM_WRITEWAIT2 0xd
+#define SDEDM_FSM_STARTPOWDOWN 0xf
+
+#define SDDATA_FIFO_WORDS 16
+
+static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
+{
+ uint32_t irq = s->status &
+ (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
+ qemu_set_irq(s->irq, !!irq);
+}
+
+static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
+{
+ SDRequest request;
+ uint8_t rsp[16];
+ int rlen;
+
+ request.cmd = s->cmd & SDCMD_CMD_MASK;
+ request.arg = s->cmdarg;
+
+ rlen = sdbus_do_command(&s->sdbus, &request, rsp);
+ if (rlen < 0) {
+ goto error;
+ }
+ if (!(s->cmd & SDCMD_NO_RESPONSE)) {
+#define RWORD(n) (((uint32_t)rsp[n] << 24) | (rsp[n + 1] << 16) \
+ | (rsp[n + 2] << 8) | rsp[n + 3])
+ if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) {
+ goto error;
+ }
+ if (rlen != 4 && rlen != 16) {
+ goto error;
+ }
+ if (rlen == 4) {
+ s->rsp[0] = RWORD(0);
+ s->rsp[1] = s->rsp[2] = s->rsp[3] = 0;
+ } else {
+ s->rsp[0] = RWORD(12);
+ s->rsp[1] = RWORD(8);
+ s->rsp[2] = RWORD(4);
+ s->rsp[3] = RWORD(0);
+ }
+#undef RWORD
+ }
+ return;
+
+error:
+ s->cmd |= SDCMD_FAIL_FLAG;
+ s->status |= SDHSTS_CMD_TIME_OUT;
+}
+
+static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value)
+{
+ int n;
+
+ if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) {
+ /* FIFO overflow */
+ return;
+ }
+ n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1);
+ s->fifo_len++;
+ s->fifo[n] = value;
+}
+
+static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s)
+{
+ uint32_t value;
+
+ if (s->fifo_len == 0) {
+ /* FIFO underflow */
+ return 0;
+ }
+ value = s->fifo[s->fifo_pos];
+ s->fifo_len--;
+ s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1);
+ return value;
+}
+
+static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
+{
+ uint32_t value = 0;
+ int n;
+ int is_read;
+
+ is_read = (s->cmd & SDCMD_READ_CMD) != 0;
+ if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) {
+ if (is_read) {
+ n = 0;
+ while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) {
+ value |= (uint32_t)sdbus_read_data(&s->sdbus) << (n * 8);
+ s->datacnt--;
+ n++;
+ if (n == 4) {
+ bcm2835_sdhost_fifo_push(s, value);
+ n = 0;
+ value = 0;
+ }
+ }
+ if (n != 0) {
+ bcm2835_sdhost_fifo_push(s, value);
+ }
+ } else { /* write */
+ n = 0;
+ while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
+ if (n == 0) {
+ value = bcm2835_sdhost_fifo_pop(s);
+ n = 4;
+ }
+ n--;
+ s->datacnt--;
+ sdbus_write_data(&s->sdbus, value & 0xff);
+ value >>= 8;
+ }
+ }
+ }
+ if (s->datacnt == 0) {
+ s->status |= SDHSTS_DATA_FLAG;
+
+ s->edm &= ~0xf;
+ s->edm |= SDEDM_FSM_DATAMODE;
+
+ if (s->config & SDHCFG_DATA_IRPT_EN) {
+ s->status |= SDHSTS_SDIO_IRPT;
+ }
+
+ if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
+ s->status |= SDHSTS_BUSY_IRPT;
+ }
+
+ if ((s->cmd & SDCMD_WRITE_CMD) && (s->config & SDHCFG_BLOCK_IRPT_EN)) {
+ s->status |= SDHSTS_BLOCK_IRPT;
+ }
+
+ bcm2835_sdhost_update_irq(s);
+ }
+
+ s->edm &= ~(0x1f << 4);
+ s->edm |= ((s->fifo_len & 0x1f) << 4);
+}
+
+static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
+ uint32_t res = 0;
+
+ switch (offset) {
+ case SDCMD:
+ res = s->cmd;
+ break;
+ case SDHSTS:
+ res = s->status;
+ break;
+ case SDRSP0:
+ res = s->rsp[0];
+ break;
+ case SDRSP1:
+ res = s->rsp[1];
+ break;
+ case SDRSP2:
+ res = s->rsp[2];
+ break;
+ case SDRSP3:
+ res = s->rsp[3];
+ break;
+ case SDEDM:
+ res = s->edm;
+ break;
+ case SDVDD:
+ res = s->vdd;
+ break;
+ case SDDATA:
+ res = bcm2835_sdhost_fifo_pop(s);
+ bcm2835_sdhost_fifo_run(s);
+ break;
+ case SDHBCT:
+ res = s->hbct;
+ break;
+ case SDHBLC:
+ res = s->hblc;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ res = 0;
+ break;
+ }
+
+ return res;
+}
+
+static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
+
+ switch (offset) {
+ case SDCMD:
+ s->cmd = value;
+ if (value & SDCMD_NEW_FLAG) {
+ bcm2835_sdhost_send_command(s);
+ bcm2835_sdhost_fifo_run(s);
+ s->cmd &= ~SDCMD_NEW_FLAG;
+ }
+ break;
+ case SDTOUT:
+ break;
+ case SDCDIV:
+ break;
+ case SDHSTS:
+ s->status &= ~value;
+ bcm2835_sdhost_update_irq(s);
+ break;
+ case SDARG:
+ s->cmdarg = value;
+ break;
+ case SDEDM:
+ if ((value & 0xf) == 0xf) {
+ /* power down */
+ value &= ~0xf;
+ }
+ s->edm = value;
+ break;
+ case SDHCFG:
+ s->config = value;
+ bcm2835_sdhost_fifo_run(s);
+ break;
+ case SDVDD:
+ s->vdd = value;
+ break;
+ case SDDATA:
+ bcm2835_sdhost_fifo_push(s, value);
+ bcm2835_sdhost_fifo_run(s);
+ break;
+ case SDHBCT:
+ s->hbct = value;
+ break;
+ case SDHBLC:
+ s->hblc = value;
+ s->datacnt = s->hblc * s->hbct;
+ bcm2835_sdhost_fifo_run(s);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps bcm2835_sdhost_ops = {
+ .read = bcm2835_sdhost_read,
+ .write = bcm2835_sdhost_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_bcm2835_sdhost = {
+ .name = TYPE_BCM2835_SDHOST,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(cmd, BCM2835SDHostState),
+ VMSTATE_UINT32(cmdarg, BCM2835SDHostState),
+ VMSTATE_UINT32(status, BCM2835SDHostState),
+ VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4),
+ VMSTATE_UINT32(config, BCM2835SDHostState),
+ VMSTATE_UINT32(edm, BCM2835SDHostState),
+ VMSTATE_UINT32(vdd, BCM2835SDHostState),
+ VMSTATE_UINT32(hbct, BCM2835SDHostState),
+ VMSTATE_UINT32(hblc, BCM2835SDHostState),
+ VMSTATE_INT32(fifo_pos, BCM2835SDHostState),
+ VMSTATE_INT32(fifo_len, BCM2835SDHostState),
+ VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN),
+ VMSTATE_UINT32(datacnt, BCM2835SDHostState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void bcm2835_sdhost_init(Object *obj)
+{
+ BCM2835SDHostState *s = BCM2835_SDHOST(obj);
+
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
+ TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
+
+ memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
+ TYPE_BCM2835_SDHOST, 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
+}
+
+static void bcm2835_sdhost_reset(DeviceState *dev)
+{
+ BCM2835SDHostState *s = BCM2835_SDHOST(dev);
+
+ s->cmd = 0;
+ s->cmdarg = 0;
+ s->edm = 0x0000c60f;
+ s->config = 0;
+ s->hbct = 0;
+ s->hblc = 0;
+ s->datacnt = 0;
+ s->fifo_pos = 0;
+ s->fifo_len = 0;
+}
+
+static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = bcm2835_sdhost_reset;
+ dc->vmsd = &vmstate_bcm2835_sdhost;
+}
+
+static TypeInfo bcm2835_sdhost_info = {
+ .name = TYPE_BCM2835_SDHOST,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835SDHostState),
+ .class_init = bcm2835_sdhost_class_init,
+ .instance_init = bcm2835_sdhost_init,
+};
+
+static const TypeInfo bcm2835_sdhost_bus_info = {
+ .name = TYPE_BCM2835_SDHOST_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+};
+
+static void bcm2835_sdhost_register_types(void)
+{
+ type_register_static(&bcm2835_sdhost_info);
+ type_register_static(&bcm2835_sdhost_bus_info);
+}
+
+type_init(bcm2835_sdhost_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller Peter Maydell
` (5 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Clement Deschamps <clement.deschamps@antfield.fr>
Provide a new function sdbus_reparent_card() in sd core for reparenting
a card from a SDBus to another one.
This function is required by the raspi platform, where the two SD
controllers can be dynamically switched.
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added a doc comment to the header file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/sd/sd.h | 11 +++++++++++
hw/sd/core.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index 79909b2..96caefe 100644
--- a/include/hw/sd/sd.h
+++ b/include/hw/sd/sd.h
@@ -140,6 +140,17 @@ uint8_t sdbus_read_data(SDBus *sd);
bool sdbus_data_ready(SDBus *sd);
bool sdbus_get_inserted(SDBus *sd);
bool sdbus_get_readonly(SDBus *sd);
+/**
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
+ * @from: controller bus to remove card from
+ * @to: controller bus to move card to
+ *
+ * Reparent an SD card, effectively unplugging it from one controller
+ * and inserting it into another. This is useful for SoCs like the
+ * bcm2835 which have two SD controllers and connect a single SD card
+ * to them, selected by the guest reprogramming GPIO line routing.
+ */
+void sdbus_reparent_card(SDBus *from, SDBus *to);
/* Functions to be used by SD devices to report back to qdevified controllers */
void sdbus_set_inserted(SDBus *sd, bool inserted);
diff --git a/hw/sd/core.c b/hw/sd/core.c
index 14c2bdf..a8f24f5 100644
--- a/hw/sd/core.c
+++ b/hw/sd/core.c
@@ -131,6 +131,36 @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
}
}
+void sdbus_reparent_card(SDBus *from, SDBus *to)
+{
+ BusChild *kid = QTAILQ_FIRST(&from->qbus.children);
+ SDState *card;
+ SDCardClass *sc;
+ bool readonly;
+
+ /* We directly reparent the card object rather than implementing this
+ * as a hotpluggable connection because we don't want to expose SD cards
+ * to users as being hotpluggable, and we can get away with it in this
+ * limited use case. This could perhaps be implemented more cleanly in
+ * future by adding support to the hotplug infrastructure for "device
+ * can be hotplugged only via code, not by user".
+ */
+
+ if (!kid) {
+ return;
+ }
+
+ card = SD_CARD(kid->child);
+ sc = SD_CARD_GET_CLASS(card);
+ readonly = sc->get_readonly(card);
+
+ sdbus_set_inserted(from, false);
+ object_unparent(OBJECT(kid));
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
+ sdbus_set_inserted(to, true);
+ sdbus_set_readonly(to, readonly);
+}
+
static const TypeInfo sd_bus_info = {
.name = TYPE_SD_BUS,
.parent = TYPE_BUS,
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers Peter Maydell
` (4 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Clement Deschamps <clement.deschamps@antfield.fr>
This adds the BCM2835 GPIO controller.
It currently implements:
- The 54 GPIOs as outputs (qemu_irq)
- The SD controller selection via alternate function of GPIOs 48-53
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/gpio/Makefile.objs | 1 +
include/hw/gpio/bcm2835_gpio.h | 39 +++++
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 393 insertions(+)
create mode 100644 include/hw/gpio/bcm2835_gpio.h
create mode 100644 hw/gpio/bcm2835_gpio.c
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index a43c7cf..fa0a72e 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -7,3 +7,4 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
obj-$(CONFIG_OMAP) += omap_gpio.o
obj-$(CONFIG_IMX) += imx_gpio.o
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
new file mode 100644
index 0000000..9f8e0c7
--- /dev/null
+++ b/include/hw/gpio/bcm2835_gpio.h
@@ -0,0 +1,39 @@
+/*
+ * Raspberry Pi (BCM2835) GPIO Controller
+ *
+ * Copyright (c) 2017 Antfield SAS
+ *
+ * Authors:
+ * Clement Deschamps <clement.deschamps@antfield.fr>
+ * Luc Michel <luc.michel@antfield.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_GPIO_H
+#define BCM2835_GPIO_H
+
+#include "hw/sd/sd.h"
+
+typedef struct BCM2835GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ /* SDBus selector */
+ SDBus sdbus;
+ SDBus *sdbus_sdhci;
+ SDBus *sdbus_sdhost;
+
+ uint8_t fsel[54];
+ uint32_t lev0, lev1;
+ uint8_t sd_fsel;
+ qemu_irq out[54];
+} BCM2835GpioState;
+
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
+#define BCM2835_GPIO(obj) \
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
+
+#endif
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
new file mode 100644
index 0000000..acc2e3c
--- /dev/null
+++ b/hw/gpio/bcm2835_gpio.c
@@ -0,0 +1,353 @@
+/*
+ * Raspberry Pi (BCM2835) GPIO Controller
+ *
+ * Copyright (c) 2017 Antfield SAS
+ *
+ * Authors:
+ * Clement Deschamps <clement.deschamps@antfield.fr>
+ * Luc Michel <luc.michel@antfield.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+#include "hw/gpio/bcm2835_gpio.h"
+
+#define GPFSEL0 0x00
+#define GPFSEL1 0x04
+#define GPFSEL2 0x08
+#define GPFSEL3 0x0C
+#define GPFSEL4 0x10
+#define GPFSEL5 0x14
+#define GPSET0 0x1C
+#define GPSET1 0x20
+#define GPCLR0 0x28
+#define GPCLR1 0x2C
+#define GPLEV0 0x34
+#define GPLEV1 0x38
+#define GPEDS0 0x40
+#define GPEDS1 0x44
+#define GPREN0 0x4C
+#define GPREN1 0x50
+#define GPFEN0 0x58
+#define GPFEN1 0x5C
+#define GPHEN0 0x64
+#define GPHEN1 0x68
+#define GPLEN0 0x70
+#define GPLEN1 0x74
+#define GPAREN0 0x7C
+#define GPAREN1 0x80
+#define GPAFEN0 0x88
+#define GPAFEN1 0x8C
+#define GPPUD 0x94
+#define GPPUDCLK0 0x98
+#define GPPUDCLK1 0x9C
+
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
+{
+ int i;
+ uint32_t value = 0;
+ for (i = 0; i < 10; i++) {
+ uint32_t index = 10 * reg + i;
+ if (index < sizeof(s->fsel)) {
+ value |= (s->fsel[index] & 0x7) << (3 * i);
+ }
+ }
+ return value;
+}
+
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
+{
+ int i;
+ for (i = 0; i < 10; i++) {
+ uint32_t index = 10 * reg + i;
+ if (index < sizeof(s->fsel)) {
+ int fsel = (value >> (3 * i)) & 0x7;
+ s->fsel[index] = fsel;
+ }
+ }
+
+ /* SD controller selection (48-53) */
+ if (s->sd_fsel != 0
+ && (s->fsel[48] == 0) /* SD_CLK_R */
+ && (s->fsel[49] == 0) /* SD_CMD_R */
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
+ ) {
+ /* SDHCI controller selected */
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
+ s->sd_fsel = 0;
+ } else if (s->sd_fsel != 4
+ && (s->fsel[48] == 4) /* SD_CLK_R */
+ && (s->fsel[49] == 4) /* SD_CMD_R */
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
+ ) {
+ /* SDHost controller selected */
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
+ s->sd_fsel = 4;
+ }
+}
+
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
+{
+ if (index >= 0 && index < 54) {
+ return s->fsel[index] == 1;
+ }
+ return 0;
+}
+
+static void gpset(BCM2835GpioState *s,
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
+{
+ uint32_t changes = val & ~*lev;
+ uint32_t cur = 1;
+
+ int i;
+ for (i = 0; i < count; i++) {
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
+ qemu_set_irq(s->out[start + i], 1);
+ }
+ cur <<= 1;
+ }
+
+ *lev |= val;
+}
+
+static void gpclr(BCM2835GpioState *s,
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
+{
+ uint32_t changes = val & *lev;
+ uint32_t cur = 1;
+
+ int i;
+ for (i = 0; i < count; i++) {
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
+ qemu_set_irq(s->out[start + i], 0);
+ }
+ cur <<= 1;
+ }
+
+ *lev &= ~val;
+}
+
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
+
+ switch (offset) {
+ case GPFSEL0:
+ case GPFSEL1:
+ case GPFSEL2:
+ case GPFSEL3:
+ case GPFSEL4:
+ case GPFSEL5:
+ return gpfsel_get(s, offset / 4);
+ case GPSET0:
+ case GPSET1:
+ /* Write Only */
+ return 0;
+ case GPCLR0:
+ case GPCLR1:
+ /* Write Only */
+ return 0;
+ case GPLEV0:
+ return s->lev0;
+ case GPLEV1:
+ return s->lev1;
+ case GPEDS0:
+ case GPEDS1:
+ case GPREN0:
+ case GPREN1:
+ case GPFEN0:
+ case GPFEN1:
+ case GPHEN0:
+ case GPHEN1:
+ case GPLEN0:
+ case GPLEN1:
+ case GPAREN0:
+ case GPAREN1:
+ case GPAFEN0:
+ case GPAFEN1:
+ case GPPUD:
+ case GPPUDCLK0:
+ case GPPUDCLK1:
+ /* Not implemented */
+ return 0;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ break;
+ }
+
+ return 0;
+}
+
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
+
+ switch (offset) {
+ case GPFSEL0:
+ case GPFSEL1:
+ case GPFSEL2:
+ case GPFSEL3:
+ case GPFSEL4:
+ case GPFSEL5:
+ gpfsel_set(s, offset / 4, value);
+ break;
+ case GPSET0:
+ gpset(s, value, 0, 32, &s->lev0);
+ break;
+ case GPSET1:
+ gpset(s, value, 32, 22, &s->lev1);
+ break;
+ case GPCLR0:
+ gpclr(s, value, 0, 32, &s->lev0);
+ break;
+ case GPCLR1:
+ gpclr(s, value, 32, 22, &s->lev1);
+ break;
+ case GPLEV0:
+ case GPLEV1:
+ /* Read Only */
+ break;
+ case GPEDS0:
+ case GPEDS1:
+ case GPREN0:
+ case GPREN1:
+ case GPFEN0:
+ case GPFEN1:
+ case GPHEN0:
+ case GPHEN1:
+ case GPLEN0:
+ case GPLEN1:
+ case GPAREN0:
+ case GPAREN1:
+ case GPAFEN0:
+ case GPAFEN1:
+ case GPPUD:
+ case GPPUDCLK0:
+ case GPPUDCLK1:
+ /* Not implemented */
+ break;
+ default:
+ goto err_out;
+ }
+ return;
+
+err_out:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+}
+
+static void bcm2835_gpio_reset(DeviceState *dev)
+{
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
+
+ int i;
+ for (i = 0; i < 6; i++) {
+ gpfsel_set(s, i, 0);
+ }
+
+ s->sd_fsel = 0;
+
+ /* SDHCI is selected by default */
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
+
+ s->lev0 = 0;
+ s->lev1 = 0;
+}
+
+static const MemoryRegionOps bcm2835_gpio_ops = {
+ .read = bcm2835_gpio_read,
+ .write = bcm2835_gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_bcm2835_gpio = {
+ .name = "bcm2835_gpio",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void bcm2835_gpio_init(Object *obj)
+{
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
+ DeviceState *dev = DEVICE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
+
+ memory_region_init_io(&s->iomem, obj,
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+ qdev_init_gpio_out(dev, s->out, 54);
+}
+
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
+{
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
+ Object *obj;
+ Error *err = NULL;
+
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
+ if (obj == NULL) {
+ error_setg(errp, "%s: required sdhci link not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+ s->sdbus_sdhci = SD_BUS(obj);
+
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
+ if (obj == NULL) {
+ error_setg(errp, "%s: required sdhost link not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+ s->sdbus_sdhost = SD_BUS(obj);
+}
+
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_bcm2835_gpio;
+ dc->realize = &bcm2835_gpio_realize;
+ dc->reset = &bcm2835_gpio_reset;
+}
+
+static const TypeInfo bcm2835_gpio_info = {
+ .name = TYPE_BCM2835_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835GpioState),
+ .instance_init = bcm2835_gpio_init,
+ .class_init = bcm2835_gpio_class_init,
+};
+
+static void bcm2835_gpio_register_types(void)
+{
+ type_register_static(&bcm2835_gpio_info);
+}
+
+type_init(bcm2835_gpio_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs Peter Maydell
` (3 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Clement Deschamps <clement.deschamps@antfield.fr>
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
For supporting the SD controller selection (alternate function of GPIOs
48-53), the bcm2835_gpio now exposes an sdbus.
It also has a link to both the sdbus of sdhci and sdhost controllers,
and the card is reparented from one bus to another when the alternate
function of GPIOs 48-53 is modified.
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/bcm2835_peripherals.h | 4 ++++
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index 31241c7..122b286 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -22,6 +22,8 @@
#include "hw/misc/bcm2835_rng.h"
#include "hw/misc/bcm2835_mbox.h"
#include "hw/sd/sdhci.h"
+#include "hw/sd/bcm2835_sdhost.h"
+#include "hw/gpio/bcm2835_gpio.h"
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
#define BCM2835_PERIPHERALS(obj) \
@@ -45,6 +47,8 @@ typedef struct BCM2835PeripheralState {
BCM2835RngState rng;
BCM2835MboxState mboxes;
SDHCIState sdhci;
+ BCM2835SDHostState sdhost;
+ BCM2835GpioState gpio;
} BCM2835PeripheralState;
#endif /* BCM2835_PERIPHERALS_H */
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 9ed22d5..369ef1e 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -96,6 +96,11 @@ static void bcm2835_peripherals_init(Object *obj)
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
+ /* SDHOST */
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
+
/* DMA Channels */
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
@@ -103,6 +108,16 @@ static void bcm2835_peripherals_init(Object *obj)
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr), &error_abort);
+
+ /* GPIO */
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
+
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
+ OBJECT(&s->sdhci.sdbus), &error_abort);
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
+ OBJECT(&s->sdhost.sdbus), &error_abort);
}
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -267,13 +282,20 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_ARASANSDIO));
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
- &err);
+
+ /* SDHOST */
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+ INTERRUPT_SDIO));
+
/* DMA Channels */
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
if (err) {
@@ -292,6 +314,23 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
BCM2835_IC_GPU_IRQ,
INTERRUPT_DMA0 + n));
}
+
+ /* GPIO */
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
+
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
}
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 18:04 ` [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID Peter Maydell
` (2 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Without any clock controller, the Linux kernel was hitting division by
zero during boot or with clk_summary:
[ 0.000000] [<c031054c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14)
[ 0.000000] [<c030ba6c>] (show_stack) from [<c05b2660>] (dump_stack+0x88/0x9c)
[ 0.000000] [<c05b2660>] (dump_stack) from [<c05b11a4>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c05b11a4>] (Ldiv0) from [<c06ad1e0>] (samsung_pll45xx_recalc_rate+0x58/0x74)
[ 0.000000] [<c06ad1e0>] (samsung_pll45xx_recalc_rate) from [<c0692ec0>] (clk_register+0x39c/0x63c)
[ 0.000000] [<c0692ec0>] (clk_register) from [<c125d360>] (samsung_clk_register_pll+0x2e0/0x3d4)
[ 0.000000] [<c125d360>] (samsung_clk_register_pll) from [<c125d7e8>] (exynos4_clk_init+0x1b0/0x5e4)
[ 0.000000] [<c125d7e8>] (exynos4_clk_init) from [<c12335f4>] (of_clk_init+0x17c/0x210)
[ 0.000000] [<c12335f4>] (of_clk_init) from [<c1204700>] (time_init+0x24/0x2c)
[ 0.000000] [<c1204700>] (time_init) from [<c1200b2c>] (start_kernel+0x24c/0x38c)
[ 0.000000] [<c1200b2c>] (start_kernel) from [<4020807c>] (0x4020807c)
Provide stub for clock controller returning reset values for PLLs.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170226200142.31169-1-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 2 +-
hw/arm/exynos4210.c | 6 ++
hw/misc/exynos4210_clk.c | 164 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 hw/misc/exynos4210_clk.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 57a4406..c8b4893 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -26,7 +26,7 @@ obj-$(CONFIG_IVSHMEM) += ivshmem.o
obj-$(CONFIG_REALVIEW) += arm_sysctl.o
obj-$(CONFIG_NSERIES) += cbus.o
obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o
+obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o
obj-$(CONFIG_IMX) += imx_ccm.o
obj-$(CONFIG_IMX) += imx31_ccm.o
obj-$(CONFIG_IMX) += imx25_ccm.o
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index be3c96d..a0ecbe8 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
@@ -74,6 +75,9 @@
/* PMU SFR base address */
#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
+/* Clock controller SFR base address */
+#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
+
/* Display controllers (FIMD) */
#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
@@ -297,6 +301,8 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
*/
sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
+ sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
+
/* PWM */
sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
s->irq_table[exynos4210_get_irq(22, 0)],
diff --git a/hw/misc/exynos4210_clk.c b/hw/misc/exynos4210_clk.c
new file mode 100644
index 0000000..81862c0
--- /dev/null
+++ b/hw/misc/exynos4210_clk.c
@@ -0,0 +1,164 @@
+/*
+ * Exynos4210 Clock Controller Emulation
+ *
+ * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+
+#define TYPE_EXYNOS4210_CLK "exynos4210.clk"
+#define EXYNOS4210_CLK(obj) \
+ OBJECT_CHECK(Exynos4210ClkState, (obj), TYPE_EXYNOS4210_CLK)
+
+#define CLK_PLL_LOCKED BIT(29)
+
+#define EXYNOS4210_CLK_REGS_MEM_SIZE 0x15104
+
+typedef struct Exynos4210Reg {
+ const char *name; /* for debug only */
+ uint32_t offset;
+ uint32_t reset_value;
+} Exynos4210Reg;
+
+/* Clock controller register base: 0x10030000 */
+static const Exynos4210Reg exynos4210_clk_regs[] = {
+ {"EPLL_LOCK", 0xc010, 0x00000fff},
+ {"VPLL_LOCK", 0xc020, 0x00000fff},
+ {"EPLL_CON0", 0xc110, 0x00300301 | CLK_PLL_LOCKED},
+ {"EPLL_CON1", 0xc114, 0x00000000},
+ {"VPLL_CON0", 0xc120, 0x00240201 | CLK_PLL_LOCKED},
+ {"VPLL_CON1", 0xc124, 0x66010464},
+ {"APLL_LOCK", 0x14000, 0x00000fff},
+ {"MPLL_LOCK", 0x14004, 0x00000fff},
+ {"APLL_CON0", 0x14100, 0x00c80601 | CLK_PLL_LOCKED},
+ {"APLL_CON1", 0x14104, 0x0000001c},
+ {"MPLL_CON0", 0x14108, 0x00c80601 | CLK_PLL_LOCKED},
+ {"MPLL_CON1", 0x1410c, 0x0000001c},
+};
+
+#define EXYNOS4210_REGS_NUM ARRAY_SIZE(exynos4210_clk_regs)
+
+typedef struct Exynos4210ClkState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ uint32_t reg[EXYNOS4210_REGS_NUM];
+} Exynos4210ClkState;
+
+static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
+ const Exynos4210Reg *regs = exynos4210_clk_regs;
+ unsigned int i;
+
+ for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
+ if (regs->offset == offset) {
+ return s->reg[i];
+ }
+ regs++;
+ }
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+}
+
+static void exynos4210_clk_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
+ const Exynos4210Reg *regs = exynos4210_clk_regs;
+ unsigned int i;
+
+ for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
+ if (regs->offset == offset) {
+ s->reg[i] = val;
+ return;
+ }
+ regs++;
+ }
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+}
+
+static const MemoryRegionOps exynos4210_clk_ops = {
+ .read = exynos4210_clk_read,
+ .write = exynos4210_clk_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false
+ }
+};
+
+static void exynos4210_clk_reset(DeviceState *dev)
+{
+ Exynos4210ClkState *s = EXYNOS4210_CLK(dev);
+ unsigned int i;
+
+ /* Set default values for registers */
+ for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
+ s->reg[i] = exynos4210_clk_regs[i].reset_value;
+ }
+}
+
+static void exynos4210_clk_init(Object *obj)
+{
+ Exynos4210ClkState *s = EXYNOS4210_CLK(obj);
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+
+ /* memory mapping */
+ memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s,
+ TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE);
+ sysbus_init_mmio(dev, &s->iomem);
+}
+
+static const VMStateDescription exynos4210_clk_vmstate = {
+ .name = TYPE_EXYNOS4210_CLK,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void exynos4210_clk_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = exynos4210_clk_reset;
+ dc->vmsd = &exynos4210_clk_vmstate;
+}
+
+static const TypeInfo exynos4210_clk_info = {
+ .name = TYPE_EXYNOS4210_CLK,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Exynos4210ClkState),
+ .instance_init = exynos4210_clk_init,
+ .class_init = exynos4210_clk_class_init,
+};
+
+static void exynos4210_clk_register(void)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n");
+ type_register_static(&exynos4210_clk_info);
+}
+
+type_init(exynos4210_clk_register)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs Peter Maydell
@ 2017-02-27 18:04 ` Peter Maydell
2017-02-27 19:14 ` [Qemu-devel] [PULL 00/30] target-arm queue no-reply
2017-02-28 12:07 ` Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-27 18:04 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
The Exynos4210 has cluster ID 0x9 in its MPIDR register (raw value
0x8000090x). If this cluster ID is not provided, then Linux kernel
cannot map DeviceTree nodes to MPIDR values resulting in kernel
warning and lack of any secondary CPUs:
DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map
...
smp: Bringing up secondary CPUs ...
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (24.00 BogoMIPS).
Provide a cluster ID so Linux will see proper MPIDR and will try to
bring the secondary CPU online.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170226200142.31169-2-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index a0ecbe8..1d2b50c 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -142,6 +142,16 @@ void exynos4210_write_secondary(ARMCPU *cpu,
info->smp_loader_start);
}
+static uint64_t exynos4210_calc_affinity(int cpu)
+{
+ uint64_t mp_affinity;
+
+ /* Exynos4210 has 0x9 as cluster ID */
+ mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu;
+
+ return mp_affinity;
+}
+
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
unsigned long ram_size)
{
@@ -167,6 +177,8 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
}
s->cpu[n] = ARM_CPU(cpuobj);
+ object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
+ "mp-affinity", &error_abort);
object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
"reset-cbar", &error_abort);
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PULL 00/30] target-arm queue
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2017-02-27 18:04 ` [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID Peter Maydell
@ 2017-02-27 19:14 ` no-reply
2017-02-28 12:07 ` Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2017-02-27 19:14 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
This series failed build test on s390x host. Please find the details below.
Message-id: 1488218699-31035-1-git-send-email-peter.maydell@linaro.org
Type: series
Subject: [Qemu-devel] [PULL 00/30] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e
echo "=== ENV ==="
env
echo "=== PACKAGES ==="
rpm -qa
echo "=== TEST BEGIN ==="
CC=$HOME/bin/cc
INSTALL=$PWD/install
BUILD=/var/tmp/patchew-qemu-build
echo -n "Using CC: "
realpath $CC
test -e $BUILD && rm -rf $BUILD
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --cc=$CC --prefix=$INSTALL
make -j4
make check -j4
make install
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1488218699-31035-1-git-send-email-peter.maydell@linaro.org -> patchew/1488218699-31035-1-git-send-email-peter.maydell@linaro.org
Switched to a new branch 'test'
fac2e4e hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
a19dfed hw/arm/exynos: Fix Linux kernel division by zero for PLLs
c49b077 bcm2835: add sdhost and gpio controllers
119282b bcm2835_gpio: add bcm2835 gpio controller
d874e6e hw/sd: add card-reparenting function
dcbc5d0 bcm2835_sdhost: add bcm2835 sdhost controller
1c9fe401 armv7m: Allow SHCSR writes to change pending and active bits
ec123a6 armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
de24aef armv7m: Check exception return consistency
aba0f63 armv7m: Extract "exception taken" code into functions
041a279 armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
87177eb armv7m: Simpler and faster exception start
8b1fa57 armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
76d49a0 armv7m: Escalate exceptions to HardFault if necessary
b554bb3 arm: gic: Remove references to NVIC
d9368b7 armv7m: Fix condition check for taking exceptions
c44de81 armv7m: Rewrite NVIC to not use any GIC code
aa72c10 armv7m: Implement reading and writing of PRIGROUP
086d1be armv7m: Rename nvic_state to NVICState
a5cf037 ARM i.MX timers: fix reset handling
4aaa21e hw/arm/virt: Add a user option to disallow ITS instantiation
45db604 cputlb: Don't assume do_unassigned_access() never returns
65c7e7f Add missing fp_access_check() to aarch64 crypto instructions
f1d750d hw/arm/virt: fix cpu object reference leak
816a1bb sd: sdhci: Remove block count enable check in single block transfers
3ea47a5 sd: sdhci: conditionally invoke multi block transfer
6d6aac0 sd: sdhci: check transfer mode register in multi block transfer
4365104 sd: sdhci: mask transfer mode register value
3c3f31d bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
f58b171 target-arm: Implement BCM2835 hardware RNG
=== OUTPUT BEGIN ===
=== ENV ===
XDG_SESSION_ID=38554
SHELL=/bin/sh
USER=fam
PATCHEW=/home/fam/patchew/patchew-cli -s http://patchew.org --nodebug
PATH=/usr/bin:/bin
PWD=/var/tmp/patchew-tester-tmp-_t3ms3un/src
LANG=en_US.UTF-8
HOME=/home/fam
SHLVL=2
LOGNAME=fam
DBUS_SESSION_BUS_ADDRESS=unix:path=/run/user/1012/bus
XDG_RUNTIME_DIR=/run/user/1012
_=/usr/bin/env
=== PACKAGES ===
gpg-pubkey-873529b8-54e386ff
xz-libs-5.2.2-2.fc24.s390x
libacl-2.2.52-11.fc24.s390x
libxshmfence-1.2-3.fc24.s390x
cdparanoia-libs-10.2-21.fc24.s390x
ustr-1.0.4-21.fc24.s390x
giflib-4.1.6-15.fc24.s390x
libusb-0.1.5-7.fc24.s390x
trousers-lib-0.3.13-6.fc24.s390x
readline-devel-6.3-8.fc24.s390x
python-srpm-macros-3-10.fc25.noarch
ncurses-base-6.0-6.20160709.fc25.noarch
gmp-6.1.1-1.fc25.s390x
chkconfig-1.8-1.fc25.s390x
libidn-1.33-1.fc25.s390x
file-5.28-4.fc25.s390x
slang-2.3.0-7.fc25.s390x
avahi-libs-0.6.32-4.fc25.s390x
libsemanage-2.5-8.fc25.s390x
perl-Unicode-Normalize-1.25-365.fc25.s390x
perl-libnet-3.10-1.fc25.noarch
perl-Thread-Queue-3.11-1.fc25.noarch
perl-podlators-4.09-1.fc25.noarch
jasper-libs-1.900.13-1.fc25.s390x
graphite2-1.3.6-1.fc25.s390x
libblkid-2.28.2-1.fc25.s390x
pkgconfig-0.29.1-1.fc25.s390x
dbus-python-1.2.4-2.fc25.s390x
alsa-lib-1.1.1-2.fc25.s390x
libgnome-keyring-3.12.0-7.fc25.s390x
yum-metadata-parser-1.1.4-17.fc25.s390x
python3-3.5.2-4.fc25.s390x
python3-slip-dbus-0.6.4-4.fc25.noarch
python2-cssselect-0.9.2-1.fc25.noarch
python-backports-1.0-8.fc25.s390x
python-magic-5.28-4.fc25.noarch
python-pycparser-2.14-7.fc25.noarch
python-fedora-0.8.0-2.fc25.noarch
createrepo_c-libs-0.10.0-6.fc25.s390x
initscripts-9.69-1.fc25.s390x
plymouth-scripts-0.9.3-0.6.20160620git0e65b86c.fc25.s390x
cronie-1.5.1-2.fc25.s390x
python2-librepo-1.7.18-3.fc25.s390x
wget-1.18-2.fc25.s390x
python3-dnf-plugins-core-0.1.21-4.fc25.noarch
at-spi2-core-2.22.0-1.fc25.s390x
libXv-1.0.11-1.fc25.s390x
dhcp-client-4.3.5-1.fc25.s390x
python2-dnf-plugins-core-0.1.21-4.fc25.noarch
parted-3.2-21.fc25.s390x
python2-ndg_httpsclient-0.4.0-4.fc25.noarch
bash-completion-2.4-1.fc25.noarch
btrfs-progs-4.6.1-1.fc25.s390x
texinfo-6.1-3.fc25.s390x
perl-Filter-1.55-366.fc25.s390x
flex-2.6.0-3.fc25.s390x
libgcc-6.3.1-1.fc25.s390x
glib2-2.50.2-1.fc25.s390x
dbus-libs-1.11.8-1.fc25.s390x
libgomp-6.3.1-1.fc25.s390x
colord-libs-1.3.4-1.fc25.s390x
perl-Encode-2.88-5.fc25.s390x
gstreamer1-1.10.2-1.fc25.s390x
cracklib-2.9.6-4.fc25.s390x
rpm-build-libs-4.13.0-6.fc25.s390x
libobjc-6.3.1-1.fc25.s390x
pcre-devel-8.40-1.fc25.s390x
mariadb-config-10.1.20-1.fc25.s390x
gcc-6.3.1-1.fc25.s390x
mesa-libGL-13.0.3-1.fc25.s390x
python3-dnf-plugin-system-upgrade-0.7.1-4.fc25.noarch
bind-libs-9.10.4-4.P5.fc25.s390x
python-osbs-client-0.33-3.fc25.noarch
NetworkManager-1.4.4-3.fc25.s390x
audit-2.7.1-1.fc25.s390x
glibc-static-2.24-4.fc25.s390x
perl-Pod-Simple-3.35-1.fc25.noarch
gdb-7.12-36.fc25.s390x
python2-simplejson-3.10.0-1.fc25.s390x
python3-sssdconfig-1.14.2-2.fc25.noarch
texlive-lib-2016-30.20160520.fc25.s390x
boost-random-1.60.0-10.fc25.s390x
brltty-5.4-2.fc25.s390x
libref_array-0.1.5-29.fc25.s390x
librados2-10.2.4-2.fc25.s390x
gnutls-dane-3.5.8-1.fc25.s390x
systemtap-client-3.1-0.20160725git91bfb36.fc25.s390x
libXrender-devel-0.9.10-1.fc25.s390x
libXi-devel-1.7.8-2.fc25.s390x
texlive-pdftex-doc-svn41149-30.fc25.noarch
tcp_wrappers-7.6-83.fc25.s390x
javapackages-tools-4.7.0-6.1.fc25.noarch
texlive-kpathsea-bin-svn40473-30.20160520.fc25.s390x
texlive-url-svn32528.3.4-30.fc25.noarch
texlive-latex-fonts-svn28888.0-30.fc25.noarch
texlive-mptopdf-bin-svn18674.0-30.20160520.fc25.noarch
texlive-underscore-svn18261.0-30.fc25.noarch
texlive-subfig-svn15878.1.3-30.fc25.noarch
texlive-dvipdfmx-def-svn40328-30.fc25.noarch
texlive-plain-svn40274-30.fc25.noarch
texlive-texlive-scripts-svn41433-30.fc25.noarch
texlive-fancyref-svn15878.0.9c-30.fc25.noarch
texlive-csquotes-svn39538-30.fc25.noarch
texlive-pxfonts-svn15878.0-30.fc25.noarch
texlive-cite-svn36428.5.5-30.fc25.noarch
texlive-section-svn20180.0-30.fc25.noarch
texlive-pslatex-svn16416.0-30.fc25.noarch
texlive-tex-gyre-math-svn41264-30.fc25.noarch
texlive-knuth-local-svn38627-30.fc25.noarch
texlive-type1cm-svn21820.0-30.fc25.noarch
texlive-finstrut-svn21719.0.5-30.fc25.noarch
texlive-ucharcat-svn38907-30.fc25.noarch
texlive-environ-svn33821.0.3-30.fc25.noarch
texlive-eso-pic-svn37925.2.0g-30.fc25.noarch
texlive-filehook-svn24280.0.5d-30.fc25.noarch
texlive-luatexbase-svn38550-30.fc25.noarch
texlive-pst-text-svn15878.1.00-30.fc25.noarch
texlive-pst-tree-svn24142.1.12-30.fc25.noarch
texlive-latex-bin-bin-svn14050.0-30.20160520.fc25.noarch
texlive-metalogo-svn18611.0.12-30.fc25.noarch
texlive-cm-super-svn15878.0-30.fc25.noarch
texlive-xetex-svn41438-30.fc25.noarch
keyutils-1.5.9-8.fc24.s390x
libcephfs_jni1-10.2.4-2.fc25.s390x
libcom_err-devel-1.43.3-1.fc25.s390x
mesa-libGLES-devel-13.0.3-1.fc25.s390x
graphite2-devel-1.3.6-1.fc25.s390x
nettle-devel-3.3-1.fc25.s390x
lzo-minilzo-2.08-8.fc24.s390x
bzip2-devel-1.0.6-21.fc25.s390x
libusbx-devel-1.0.21-1.fc25.s390x
SDL2-devel-2.0.5-2.fc25.s390x
virglrenderer-devel-0.5.0-1.20160411git61846f92f.fc25.s390x
glib2-static-2.50.2-1.fc25.s390x
mesa-libgbm-devel-13.0.3-1.fc25.s390x
acpica-tools-20160831-1.fc25.s390x
gdk-pixbuf2-2.36.4-1.fc25.s390x
nss-softokn-3.28.1-1.0.fc25.s390x
python3-dnf-1.1.10-5.fc25.noarch
python-gluster-3.9.1-1.fc25.noarch
perl-IO-1.36-382.fc25.s390x
glusterfs-devel-3.9.1-1.fc25.s390x
gtk3-3.22.7-1.fc25.s390x
vim-enhanced-8.0.206-1.fc25.s390x
nss-tools-3.28.1-1.3.fc25.s390x
libmicrohttpd-0.9.52-1.fc25.s390x
gpg-pubkey-a29cb19c-53bcbba6
libaio-0.3.110-6.fc24.s390x
m4-1.4.17-9.fc24.s390x
libfontenc-1.1.3-3.fc24.s390x
lzo-2.08-8.fc24.s390x
isl-0.14-5.fc24.s390x
libXau-1.0.8-6.fc24.s390x
liblockfile-1.09-4.fc24.s390x
linux-atm-libs-2.5.1-14.fc24.s390x
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binutils-2.26.1-1.fc25.s390x
lcms2-2.8-2.fc25.s390x
libcomps-0.1.7-5.fc25.s390x
less-481-6.fc25.s390x
apr-1.5.2-4.fc25.s390x
perl-constant-1.33-367.fc25.noarch
perl-Data-Dumper-2.161-1.fc25.s390x
ipcalc-0.1.8-1.fc25.s390x
perl-Pod-Perldoc-3.27-1.fc25.noarch
libteam-1.26-1.fc25.s390x
gmp-c++-6.1.1-1.fc25.s390x
fontconfig-2.12.1-1.fc25.s390x
enchant-1.6.0-14.fc25.s390x
json-glib-1.2.2-1.fc25.s390x
pyliblzma-0.5.3-16.fc25.s390x
libsepol-devel-2.5-10.fc25.s390x
python3-libs-3.5.2-4.fc25.s390x
python3-ordered-set-2.0.0-4.fc25.noarch
python3-rpmconf-1.0.18-2.fc25.noarch
python-ipaddress-1.0.16-3.fc25.noarch
python2-kerberos-1.2.5-1.fc25.s390x
python2-pysocks-1.5.6-5.fc25.noarch
fipscheck-lib-1.4.1-11.fc25.s390x
libatomic_ops-7.4.4-1.fc25.s390x
net-snmp-agent-libs-5.7.3-13.fc25.s390x
util-linux-2.28.2-1.fc25.s390x
dracut-044-78.fc25.s390x
python2-pygpgme-0.3-18.fc25.s390x
libsoup-2.56.0-2.fc25.s390x
orc-0.4.26-1.fc25.s390x
yum-utils-1.1.31-511.fc25.noarch
libXrender-0.9.10-1.fc25.s390x
libXrandr-1.5.1-1.fc25.s390x
go-srpm-macros-2-7.fc25.noarch
gnupg2-smime-2.1.13-2.fc25.s390x
guile-devel-2.0.13-1.fc25.s390x
uboot-tools-2016.09.01-2.fc25.s390x
pykickstart-2.32-1.fc25.noarch
python-bunch-1.0.1-9.fc25.noarch
perl-generators-1.10-1.fc25.noarch
perl-Mozilla-CA-20160104-3.fc25.noarch
glibc-all-langpacks-2.24-4.fc25.s390x
bzip2-libs-1.0.6-21.fc25.s390x
libpng-1.6.27-1.fc25.s390x
libtiff-4.0.7-1.fc25.s390x
desktop-file-utils-0.23-2.fc25.s390x
python2-cccolutils-1.4-1.fc25.s390x
libcurl-7.51.0-4.fc25.s390x
rpm-plugin-systemd-inhibit-4.13.0-6.fc25.s390x
cups-libs-2.2.0-5.fc25.s390x
python2-lxml-3.7.2-1.fc25.s390x
redhat-rpm-config-45-1.fc25.noarch
elfutils-libs-0.168-1.fc25.s390x
device-mapper-event-libs-1.02.136-3.fc25.s390x
lvm2-libs-2.02.167-3.fc25.s390x
elfutils-0.168-1.fc25.s390x
openssh-7.4p1-1.fc25.s390x
python2-gitdb-2.0.0-1.fc25.noarch
openssh-server-7.4p1-1.fc25.s390x
gcc-gfortran-6.3.1-1.fc25.s390x
rpm-devel-4.13.0-6.fc25.s390x
libselinux-python-2.5-13.fc25.s390x
openjpeg2-2.1.2-3.fc25.s390x
js-jquery-2.2.4-1.fc25.noarch
boost-thread-1.60.0-10.fc25.s390x
json-c-0.12-7.fc24.s390x
ghostscript-x11-9.20-5.fc25.s390x
libdrm-devel-2.4.74-1.fc25.s390x
libuuid-devel-2.28.2-1.fc25.s390x
librbd-devel-10.2.4-2.fc25.s390x
libXcursor-devel-1.1.14-6.fc24.s390x
python3-beautifulsoup4-4.5.3-1.fc25.noarch
texlive-kpathsea-svn41139-30.fc25.noarch
texlive-amsmath-svn41561-30.fc25.noarch
texlive-thumbpdf-svn34621.3.16-30.fc25.noarch
texlive-multido-svn18302.1.42-30.fc25.noarch
texlive-float-svn15878.1.3d-30.fc25.noarch
texlive-psnfss-svn33946.9.2a-30.fc25.noarch
texlive-wasy-svn35831.0-30.fc25.noarch
texlive-makeindex-svn40768-30.fc25.noarch
texlive-pdftex-svn41149-30.fc25.noarch
texlive-enumitem-svn24146.3.5.2-30.fc25.noarch
texlive-microtype-svn41127-30.fc25.noarch
texlive-helvetic-svn31835.0-30.fc25.noarch
texlive-times-svn35058.0-30.fc25.noarch
texlive-mdwtools-svn15878.1.05.4-30.fc25.noarch
texlive-babel-english-svn30264.3.3p-30.fc25.noarch
texlive-cmextra-svn32831.0-30.fc25.noarch
texlive-enctex-svn34957.0-30.fc25.noarch
texlive-texlive-docindex-svn41430-30.fc25.noarch
texlive-ifetex-svn24853.1.2-30.fc25.noarch
texlive-mparhack-svn15878.1.4-30.fc25.noarch
texlive-paralist-svn39247-30.fc25.noarch
texlive-algorithms-svn38085.0.1-30.fc25.noarch
texlive-geometry-svn19716.5.6-30.fc25.noarch
texlive-fontspec-svn41262-30.fc25.noarch
texlive-oberdiek-svn41346-30.fc25.noarch
texlive-pst-eps-svn15878.1.0-30.fc25.noarch
texlive-pstricks-svn41321-30.fc25.noarch
texlive-pst-blur-svn15878.2.0-30.fc25.noarch
texlive-jknapltx-svn19440.0-30.fc25.noarch
texlive-breqn-svn38099.0.98d-30.fc25.noarch
texlive-collection-basic-svn41149-30.20160520.fc25.noarch
latex2html-2012-7.fc24.noarch
lksctp-tools-1.0.16-5.fc24.s390x
vte291-0.46.1-1.fc25.s390x
openssl-devel-1.0.2j-3.fc25.s390x
at-spi2-core-devel-2.22.0-1.fc25.s390x
libfdt-1.4.2-1.fc25.s390x
libXft-devel-2.3.2-4.fc24.s390x
libattr-devel-2.4.47-16.fc24.s390x
libiscsi-devel-1.15.0-2.fc24.s390x
gettext-0.19.8.1-3.fc25.s390x
libjpeg-turbo-devel-1.5.1-0.fc25.s390x
glusterfs-libs-3.9.1-1.fc25.s390x
glusterfs-api-3.9.1-1.fc25.s390x
hawkey-0.6.3-6.1.fc25.s390x
nss-softokn-devel-3.28.1-1.0.fc25.s390x
glusterfs-cli-3.9.1-1.fc25.s390x
vim-common-8.0.206-1.fc25.s390x
libX11-1.6.4-4.fc25.s390x
pulseaudio-libs-devel-10.0-2.fc25.s390x
dnf-yum-1.1.10-5.fc25.noarch
tzdata-java-2016j-2.fc25.noarch
ccache-3.3.3-1.fc25.s390x
gpg-pubkey-8e1431d5-53bcbac7
zlib-1.2.8-10.fc24.s390x
sed-4.2.2-15.fc24.s390x
p11-kit-0.23.2-2.fc24.s390x
psmisc-22.21-8.fc24.s390x
gpm-libs-1.20.7-9.fc24.s390x
zip-3.0-16.fc24.s390x
hostname-3.15-7.fc24.s390x
libyubikey-1.13-2.fc24.s390x
sg3_utils-libs-1.41-3.fc24.s390x
polkit-pkla-compat-0.1-7.fc24.s390x
passwd-0.79-8.fc24.s390x
trousers-0.3.13-6.fc24.s390x
grubby-8.40-3.fc24.s390x
rootfiles-8.1-19.fc24.noarch
python-rpm-macros-3-10.fc25.noarch
info-6.1-3.fc25.s390x
libuuid-2.28.2-1.fc25.s390x
iptables-libs-1.6.0-2.fc25.s390x
nettle-3.3-1.fc25.s390x
jansson-2.9-1.fc25.s390x
libksba-1.3.5-1.fc25.s390x
perl-Text-ParseWords-3.30-365.fc25.noarch
perl-PathTools-3.63-366.fc25.s390x
perl-File-Temp-0.23.04-365.fc25.noarch
fuse-libs-2.9.7-1.fc25.s390x
perl-Pod-Escapes-1.07-365.fc25.noarch
perl-Term-ANSIColor-4.05-2.fc25.noarch
perl-URI-1.71-5.fc25.noarch
libXfont-1.5.2-1.fc25.s390x
crypto-policies-20160921-2.git75b9b04.fc25.noarch
python-six-1.10.0-3.fc25.noarch
dbus-glib-0.108-1.fc25.s390x
gobject-introspection-1.50.0-1.fc25.s390x
libpwquality-1.3.0-6.fc25.s390x
python-gobject-base-3.22.0-1.fc25.s390x
python-html5lib-0.999-9.fc25.noarch
python3-dbus-1.2.4-2.fc25.s390x
python3-chardet-2.3.0-1.fc25.noarch
python3-urllib3-1.15.1-3.fc25.noarch
python-offtrac-0.1.0-7.fc25.noarch
python2-cryptography-1.5.3-3.fc25.s390x
python2-requests-kerberos-0.10.0-2.fc25.noarch
libserf-1.3.9-1.fc25.s390x
libdatrie-0.2.9-3.fc25.s390x
s390utils-base-1.36.0-1.fc25.s390x
kpartx-0.4.9-83.fc25.s390x
s390utils-cpuplugd-1.36.0-1.fc25.s390x
rpmconf-1.0.18-2.fc25.noarch
s390utils-osasnmpd-1.36.0-1.fc25.s390x
python-dnf-plugins-extras-common-0.0.12-4.fc25.noarch
pango-1.40.3-1.fc25.s390x
fpc-srpm-macros-1.0-1.fc25.noarch
kernel-core-4.8.8-300.fc25.s390x
fedora-upgrade-25.2-1.fc25.noarch
net-tools-2.0-0.38.20160329git.fc25.s390x
libuser-0.62-4.fc25.s390x
screen-4.4.0-4.fc25.s390x
man-db-2.7.5-3.fc25.s390x
sqlite-3.14.2-1.fc25.s390x
python-systemd-doc-232-1.fc25.s390x
pcre-8.40-1.fc25.s390x
libdb-5.3.28-16.fc25.s390x
lz4-1.7.5-1.fc25.s390x
tar-1.29-3.fc25.s390x
emacs-common-25.1-3.fc25.s390x
perl-threads-shared-1.54-1.fc25.s390x
unzip-6.0-31.fc25.s390x
mesa-libglapi-13.0.3-1.fc25.s390x
rpm-libs-4.13.0-6.fc25.s390x
selinux-policy-3.13.1-225.6.fc25.noarch
pcre-utf16-8.40-1.fc25.s390x
bodhi-client-0.9.12.2-6.fc25.noarch
rpmlint-1.9-5.fc25.noarch
glibc-headers-2.24-4.fc25.s390x
dbus-1.11.8-1.fc25.s390x
kernel-core-4.9.3-200.fc25.s390x
cairo-1.14.8-1.fc25.s390x
ca-certificates-2017.2.11-1.0.fc25.noarch
openssh-clients-7.4p1-1.fc25.s390x
python2-GitPython-2.1.1-2.fc25.noarch
mariadb-libs-10.1.20-1.fc25.s390x
NetworkManager-glib-1.4.4-3.fc25.s390x
gcc-go-6.3.1-1.fc25.s390x
cracklib-dicts-2.9.6-4.fc25.s390x
iproute-tc-4.6.0-6.fc25.s390x
libselinux-python3-2.5-13.fc25.s390x
strace-4.15-1.fc25.s390x
python2-enchant-1.6.8-1.fc25.noarch
boost-iostreams-1.60.0-10.fc25.s390x
bluez-libs-5.43-1.fc25.s390x
ghostscript-9.20-5.fc25.s390x
userspace-rcu-0.9.2-2.fc25.s390x
mesa-libwayland-egl-devel-13.0.3-1.fc25.s390x
libXext-devel-1.3.3-4.fc24.s390x
libXrandr-devel-1.5.1-1.fc25.s390x
perl-XML-XPath-1.39-1.fc25.noarch
python3-lxml-3.7.2-1.fc25.s390x
texlive-texlive.infra-bin-svn40312-30.20160520.fc25.s390x
texlive-ifxetex-svn19685.0.5-30.fc25.noarch
texlive-thumbpdf-bin-svn6898.0-30.20160520.fc25.noarch
texlive-babelbib-svn25245.1.31-30.fc25.noarch
texlive-index-svn24099.4.1beta-30.fc25.noarch
texlive-caption-svn41409-30.fc25.noarch
texlive-bibtex-bin-svn40473-30.20160520.fc25.s390x
texlive-mfware-bin-svn40473-30.20160520.fc25.s390x
texlive-texconfig-svn40768-30.fc25.noarch
texlive-footmisc-svn23330.5.5b-30.fc25.noarch
texlive-psfrag-svn15878.3.04-30.fc25.noarch
texlive-eurosym-svn17265.1.4_subrfix-30.fc25.noarch
texlive-symbol-svn31835.0-30.fc25.noarch
texlive-euenc-svn19795.0.1h-30.fc25.noarch
texlive-textcase-svn15878.0-30.fc25.noarch
texlive-charter-svn15878.0-30.fc25.noarch
texlive-wasysym-svn15878.2.0-30.fc25.noarch
texlive-mflogo-svn38628-30.fc25.noarch
texlive-soul-svn15878.2.4-30.fc25.noarch
texlive-marginnote-svn41382-30.fc25.noarch
texlive-filecontents-svn24250.1.3-30.fc25.noarch
texlive-tipa-svn29349.1.3-30.fc25.noarch
texlive-xcolor-svn41044-30.fc25.noarch
texlive-breakurl-svn29901.1.40-30.fc25.noarch
texlive-attachfile-svn38830-30.fc25.noarch
texlive-pst-coil-svn37377.1.07-30.fc25.noarch
texlive-auto-pst-pdf-svn23723.0.6-30.fc25.noarch
texlive-ctable-svn38672-30.fc25.noarch
texlive-extsizes-svn17263.1.4a-30.fc25.noarch
texlive-beamer-svn36461.3.36-30.fc25.noarch
texlive-dvipdfmx-bin-svn40273-30.20160520.fc25.s390x
netpbm-progs-10.76.00-2.fc25.s390x
vte-profile-0.46.1-1.fc25.s390x
krb5-devel-1.14.4-4.fc25.s390x
dbus-devel-1.11.8-1.fc25.s390x
sqlite-devel-3.14.2-1.fc25.s390x
libiscsi-1.15.0-2.fc24.s390x
fontconfig-devel-2.12.1-1.fc25.s390x
libfdt-devel-1.4.2-1.fc25.s390x
ceph-devel-compat-10.2.4-2.fc25.s390x
zlib-static-1.2.8-10.fc24.s390x
chrpath-0.16-3.fc24.s390x
python-2.7.13-1.fc25.s390x
nss-3.28.1-1.3.fc25.s390x
python2-hawkey-0.6.3-6.1.fc25.s390x
gdk-pixbuf2-modules-2.36.4-1.fc25.s390x
perl-Git-2.9.3-2.fc25.noarch
kernel-core-4.9.5-200.fc25.s390x
publicsuffix-list-dafsa-20170116-1.fc25.noarch
perl-SelfLoader-1.23-382.fc25.noarch
perl-open-1.10-382.fc25.noarch
gpgme-1.8.0-8.fc25.s390x
=== TEST BEGIN ===
Using CC: /home/fam/bin/cc
Install prefix /var/tmp/patchew-tester-tmp-_t3ms3un/src/install
BIOS directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/share/qemu
binary directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/bin
library directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/lib
module directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/lib/qemu
libexec directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/libexec
include directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/include
config directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/etc
local state directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/var
Manual directory /var/tmp/patchew-tester-tmp-_t3ms3un/src/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /var/tmp/patchew-tester-tmp-_t3ms3un/src
C compiler /home/fam/bin/cc
Host C compiler cc
C++ compiler c++
Objective-C compiler /home/fam/bin/cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -Werror -DHAS_LIBSSH2_SFTP_FSYNC -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -D_GNU_SOURCE -m64 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/include/p11-kit-1 -I/usr/include/libpng16 -I/usr/include/cacard -I/usr/include/nss3 -I/usr/include/nspr4 -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/libusb-1.0
LDFLAGS -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU s390x
host big endian yes
target list aarch64-softmmu alpha-softmmu arm-softmmu cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblazeel-softmmu microblaze-softmmu mips64el-softmmu mips64-softmmu mipsel-softmmu mips-softmmu moxie-softmmu nios2-softmmu or1k-softmmu ppc64-softmmu ppcemb-softmmu ppc-softmmu s390x-softmmu sh4eb-softmmu sh4-softmmu sparc64-softmmu sparc-softmmu tricore-softmmu unicore32-softmmu x86_64-softmmu xtensaeb-softmmu xtensa-softmmu aarch64-linux-user alpha-linux-user armeb-linux-user arm-linux-user cris-linux-user hppa-linux-user i386-linux-user m68k-linux-user microblazeel-linux-user microblaze-linux-user mips64el-linux-user mips64-linux-user mipsel-linux-user mips-linux-user mipsn32el-linux-user mipsn32-linux-user nios2-linux-user or1k-linux-user ppc64abi32-linux-user ppc64le-linux-user ppc64-linux-user ppc-linux-user s390x-linux-user sh4eb-linux-user sh4-linux-user sparc32plus-linux-user sparc64-linux-user sparc-linux-user tilegx-linux-user x86_64-linux-user
tcg debug enabled no
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
pixman system
SDL support yes (2.0.5)
GTK support yes (3.22.7)
GTK GL support yes
VTE support yes (0.46.1)
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.3)
nettle kdf yes
libtasn1 yes
curses support yes
virgl support yes
curl support yes
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support yes
VNC support yes
VNC SASL support yes
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support yes
bluez support yes
Documentation yes
PIE no
vde support no
netmap support no
Linux AIO support yes
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
RDMA support no
TCG interpreter no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support yes
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log
spice support no
rbd support yes
xfsctl support no
smartcard support yes
libusb yes
usb net redir yes
OpenGL support yes
OpenGL dmabufs yes
libiscsi support yes
libnfs support yes
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support yes
Archipelago support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
QOM debugging yes
lzo support yes
snappy support yes
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
GEN aarch64-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak
GEN i386-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak
GEN lm32-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak
GEN m68k-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak
GEN microblazeel-softmmu/config-devices.mak.tmp
GEN lm32-softmmu/config-devices.mak
GEN microblaze-softmmu/config-devices.mak.tmp
GEN i386-softmmu/config-devices.mak
GEN m68k-softmmu/config-devices.mak
GEN mips64el-softmmu/config-devices.mak.tmp
GEN microblazeel-softmmu/config-devices.mak
GEN microblaze-softmmu/config-devices.mak
GEN mips64-softmmu/config-devices.mak.tmp
GEN mips-softmmu/config-devices.mak.tmp
GEN mipsel-softmmu/config-devices.mak.tmp
GEN mips64el-softmmu/config-devices.mak
GEN moxie-softmmu/config-devices.mak.tmp
GEN mips-softmmu/config-devices.mak
GEN mipsel-softmmu/config-devices.mak
GEN mips64-softmmu/config-devices.mak
GEN nios2-softmmu/config-devices.mak.tmp
GEN or1k-softmmu/config-devices.mak.tmp
GEN ppc64-softmmu/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak
GEN ppcemb-softmmu/config-devices.mak.tmp
GEN nios2-softmmu/config-devices.mak
GEN ppc-softmmu/config-devices.mak.tmp
GEN or1k-softmmu/config-devices.mak
GEN s390x-softmmu/config-devices.mak.tmp
GEN ppc64-softmmu/config-devices.mak
GEN ppcemb-softmmu/config-devices.mak
GEN sh4eb-softmmu/config-devices.mak.tmp
GEN s390x-softmmu/config-devices.mak
GEN sparc64-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak
GEN sh4eb-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak
GEN unicore32-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak
GEN sparc64-softmmu/config-devices.mak
GEN x86_64-softmmu/config-devices.mak.tmp
GEN unicore32-softmmu/config-devices.mak
GEN xtensa-softmmu/config-devices.mak.tmp
GEN aarch64-linux-user/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak.tmp
GEN aarch64-linux-user/config-devices.mak
GEN xtensa-softmmu/config-devices.mak
GEN alpha-linux-user/config-devices.mak.tmp
GEN armeb-linux-user/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak
GEN arm-linux-user/config-devices.mak.tmp
GEN alpha-linux-user/config-devices.mak
GEN cris-linux-user/config-devices.mak.tmp
GEN x86_64-softmmu/config-devices.mak
GEN armeb-linux-user/config-devices.mak
GEN hppa-linux-user/config-devices.mak.tmp
GEN i386-linux-user/config-devices.mak.tmp
GEN cris-linux-user/config-devices.mak
GEN hppa-linux-user/config-devices.mak
GEN arm-linux-user/config-devices.mak
GEN m68k-linux-user/config-devices.mak.tmp
GEN microblazeel-linux-user/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak.tmp
GEN i386-linux-user/config-devices.mak
GEN mips64el-linux-user/config-devices.mak.tmp
GEN m68k-linux-user/config-devices.mak
GEN mips64-linux-user/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak
GEN microblazeel-linux-user/config-devices.mak
GEN mips64el-linux-user/config-devices.mak
GEN mipsel-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak
GEN mips-linux-user/config-devices.mak.tmp
GEN mipsn32el-linux-user/config-devices.mak.tmp
GEN mipsn32-linux-user/config-devices.mak.tmp
GEN mipsel-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak.tmp
GEN mips-linux-user/config-devices.mak
GEN mipsn32el-linux-user/config-devices.mak
GEN or1k-linux-user/config-devices.mak.tmp
GEN mipsn32-linux-user/config-devices.mak
GEN ppc64abi32-linux-user/config-devices.mak.tmp
GEN nios2-linux-user/config-devices.mak
GEN ppc64le-linux-user/config-devices.mak.tmp
GEN ppc64-linux-user/config-devices.mak.tmp
GEN ppc64le-linux-user/config-devices.mak
GEN ppc64abi32-linux-user/config-devices.mak
GEN or1k-linux-user/config-devices.mak
GEN ppc-linux-user/config-devices.mak.tmp
GEN s390x-linux-user/config-devices.mak.tmp
GEN sh4eb-linux-user/config-devices.mak.tmp
GEN ppc64-linux-user/config-devices.mak
GEN sh4-linux-user/config-devices.mak.tmp
GEN s390x-linux-user/config-devices.mak
GEN sparc32plus-linux-user/config-devices.mak.tmp
GEN sh4eb-linux-user/config-devices.mak
GEN ppc-linux-user/config-devices.mak
GEN sparc64-linux-user/config-devices.mak.tmp
GEN sparc-linux-user/config-devices.mak.tmp
GEN sh4-linux-user/config-devices.mak
GEN sparc32plus-linux-user/config-devices.mak
GEN x86_64-linux-user/config-devices.mak.tmp
GEN sparc-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak.tmp
GEN sparc64-linux-user/config-devices.mak
GEN config-host.h
GEN x86_64-linux-user/config-devices.mak
GEN qemu-options.def
GEN tilegx-linux-user/config-devices.mak
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN qmp-introspect.h
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN backends/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/i386/trace.h
GEN hw/mem/trace.h
GEN hw/9pfs/trace.h
GEN hw/i386/xen/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN target/arm/trace.h
GEN net/trace.h
GEN target/sparc/trace.h
GEN target/i386/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN config-all-devices.mak
CC tests/qemu-iotests/socket_scm_helper.o
GEN version.texi
GEN qemu-img-cmds.texi
GEN qemu-options.texi
GEN qemu-monitor.texi
GEN qemu-monitor-info.texi
GEN qemu-img.1
GEN qemu-nbd.8
GEN qemu-ga.8
GEN qemu-qapi.texi
GEN qemu-ga-qapi.texi
GEN fsdev/virtfs-proxy-helper.1
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN backends/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/scsi/trace.c
GEN hw/usb/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/acpi/trace.c
GEN hw/vfio/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/sparc/trace.c
GEN target/i386/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN qmp-introspect.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/string-input-visitor.o
CC qapi/qmp-dispatch.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-posix.o
CC util/compatfd.o
CC util/event_notifier-posix.o
CC util/mmap-alloc.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/host-utils.o
CC util/module.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/qemu-option.o
CC util/notify.o
CC util/qemu-progress.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/timed-average.o
CC util/buffer.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/cpu-get-clock.o
CC stubs/clock-warp.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/linux-aio.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC qemu-io-cmds.o
CC blockjob.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qed.o
CC block/qed-gencb.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/qapi.o
CC block/snapshot.o
CC block/file-posix.o
CC block/linux-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/iscsi-opts.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC block/iscsi.o
CC block/nfs.o
CC block/curl.o
CC block/rbd.o
CC block/gluster.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/hmac-nettle.o
CC crypto/aes.o
CC crypto/cipher.o
CC crypto/desrfb.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/random-gnutls.o
CC crypto/secret.o
CC crypto/pbkdf.o
CC crypto/ivgen.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-tls.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC fsdev/virtfs-proxy-helper.o
CC fsdev/9p-marshal.o
CC fsdev/9p-iov-marshal.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC page_cache.o
CC accel.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
GEN qmp-marshal.c
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/mixeng.o
CC audio/wavaudio.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/msmouse.o
CC backends/rng-random.o
CC backends/wctablet.o
CC backends/testdev.o
CC backends/baum.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC disas/alpha.o
CC disas/arm.o
CXX disas/arm-a64.o
CC disas/cris.o
CC disas/hppa.o
CC disas/i386.o
CC disas/m68k.o
CC disas/microblaze.o
CC disas/mips.o
CC disas/nios2.o
CC disas/moxie.o
CC disas/ppc.o
CC disas/s390.o
CC disas/sh4.o
CC disas/sparc.o
CC disas/lm32.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC fsdev/qemu-fsdev.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-dummy.o
CC hw/9pfs/9p-local.o
CC hw/9pfs/9p.o
CC hw/9pfs/9p-xattr.o
CC hw/9pfs/9p-xattr-user.o
CC hw/9pfs/9p-posix-acl.o
CC hw/9pfs/coth.o
CC hw/9pfs/cofs.o
CC hw/9pfs/codir.o
CC hw/9pfs/cofile.o
CC hw/9pfs/coxattr.o
CC hw/9pfs/9p-synth.o
CC hw/9pfs/9p-handle.o
CC hw/9pfs/9p-proxy.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/cs4231.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/milkymist-ac97.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/fdc.o
CC hw/block/hd-geometry.o
CC hw/block/nand.o
CC hw/block/m25p80.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/escc.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/xilinx_uartlite.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/etraxfs_ser.o
CC hw/char/debugcon.o
CC hw/char/grlib_apbuart.o
CC hw/char/imx_serial.o
CC hw/char/lm32_juart.o
CC hw/char/lm32_uart.o
CC hw/char/milkymist-uart.o
CC hw/char/sclpconsole.o
CC hw/char/sclpconsole-lm.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/empty_slot.o
CC hw/core/stream.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/loader-fit.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/g364fb.o
CC hw/display/jazz_led.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vga-isa-mm.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/milkymist-vgafb.o
CC hw/display/tc6393xb.o
CC hw/dma/puv3_dma.o
CC hw/display/milkymist-tmu2.o
CC hw/dma/rc4030.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i82374.o
CC hw/dma/i8257.o
CC hw/dma/xilinx_axidma.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/dma/etraxfs_dma.o
CC hw/dma/sparc32_dma.o
CC hw/dma/sun4m_iommu.o
CC hw/gpio/pl061.o
CC hw/gpio/max7310.o
CC hw/gpio/puv3_gpio.o
CC hw/gpio/zaurus.o
CC hw/gpio/mpc8xxx.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/cmd646.o
CC hw/ide/macio.o
CC hw/ide/mmio.o
CC hw/ide/via.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/adb.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/stellaris_input.o
CC hw/input/ps2.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/heathrow_pic.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/puv3_intc.o
CC hw/intc/xilinx_intc.o
CC hw/intc/imx_avic.o
CC hw/intc/etraxfs_pic.o
CC hw/intc/lm32_pic.o
CC hw/intc/realview_gic.o
CC hw/intc/slavio_intctl.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/openpic.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/isa/i82378.o
CC hw/isa/pc87312.o
CC hw/isa/piix4.o
CC hw/mem/pc-dimm.o
CC hw/isa/vt82c686.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pci-testdev.o
CC hw/misc/pc-testdev.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/misc/puv3_pm.o
CC hw/misc/macio/macio.o
CC hw/misc/macio/cuda.o
CC hw/misc/macio/mac_dbdma.o
CC hw/net/dp8393x.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/opencores_eth.o
CC hw/net/xgmac.o
CC hw/net/mipsnet.o
CC hw/net/xilinx_axienet.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/lance.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/ds1225y.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/mac_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/dec.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/prep.o
CC hw/pci-host/grackle.o
CC hw/pci-host/uninorth.o
CC hw/pci-host/ppce500.o
CC hw/pci-host/apb.o
CC hw/pci-host/versatile.o
CC hw/pci-host/bonito.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci-host/xilinx-pcie.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/smbios/smbios.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/xilinx_spi.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/m48t59.o
CC hw/timer/m48t59-isa.o
CC hw/timer/pl031.o
CC hw/timer/puv3_ost.o
CC hw/timer/twl92230.o
CC hw/timer/xilinx_timer.o
CC hw/timer/slavio_timer.o
CC hw/timer/etraxfs_timer.o
CC hw/timer/grlib_gptimer.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/lm32_timer.o
CC hw/timer/milkymist-sysctl.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/sun4v-rtc.o
CC hw/tpm/tpm_tis.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-network.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/ccid-card-passthru.o
CC hw/usb/ccid-card-emulated.o
CC hw/usb/dev-mtp.o
CC hw/usb/redirect.o
CC hw/usb/quirks.o
CC hw/usb/host-libusb.o
CC hw/usb/host-legacy.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_diag288.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/fd.o
CC migration/socket.o
CC migration/exec.o
CC migration/tls.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/qemu-file.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/tap.o
CC net/vhost-user.o
CC net/tap-linux.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-events.o
CC replay/replay-internal.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/sdl2-input.o
CC ui/sdl2.o
CC ui/sdl2-2d.o
CC ui/sdl2-gl.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-auth-sasl.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
CC ui/shader.o
VERT ui/shader/texture-blit-vert.h
FRAG ui/shader/texture-blit-frag.h
CC ui/egl-helpers.o
CC ui/egl-context.o
CC ui/gtk-gl-area.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
CCAS s390-ccw/start.o
LINK tests/qemu-iotests/socket_scm_helper
GEN qemu-doc.html
CC s390-ccw/main.o
GEN qemu-doc.txt
GEN qemu.1
CC s390-ccw/bootmap.o
CC s390-ccw/sclp-ascii.o
CC s390-ccw/virtio.o
GEN docs/qemu-qmp-ref.html
CC s390-ccw/virtio-scsi.o
BUILD s390-ccw/s390-ccw.elf
STRIP s390-ccw/s390-ccw.img
GEN docs/qemu-qmp-ref.txt
GEN docs/qemu-qmp-ref.7
GEN docs/qemu-ga-ref.html
GEN docs/qemu-ga-ref.txt
GEN docs/qemu-ga-ref.7
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-posix.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
AR libqemustub.a
CC qemu-img.o
CC qmp-marshal.o
CC ui/console-gl.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC backends/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/intc/trace.o
CC hw/char/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
AR libqemuutil.a
LINK qemu-ga
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-img
LINK qemu-io
LINK fsdev/virtfs-proxy-helper
LINK qemu-bridge-helper
GEN alpha-softmmu/hmp-commands.h
GEN cris-softmmu/hmp-commands.h
GEN cris-softmmu/hmp-commands-info.h
GEN cris-softmmu/config-target.h
CC cris-softmmu/exec.o
GEN alpha-softmmu/hmp-commands-info.h
GEN alpha-softmmu/config-target.h
GEN arm-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands.h
GEN arm-softmmu/hmp-commands-info.h
CC alpha-softmmu/exec.o
GEN aarch64-softmmu/hmp-commands-info.h
GEN arm-softmmu/config-target.h
GEN aarch64-softmmu/config-target.h
CC arm-softmmu/exec.o
CC aarch64-softmmu/exec.o
CC cris-softmmu/translate-all.o
CC alpha-softmmu/translate-all.o
CC aarch64-softmmu/translate-all.o
CC cris-softmmu/cpu-exec.o
CC arm-softmmu/translate-all.o
CC alpha-softmmu/cpu-exec.o
CC cris-softmmu/translate-common.o
CC aarch64-softmmu/cpu-exec.o
CC alpha-softmmu/translate-common.o
CC cris-softmmu/cpu-exec-common.o
CC arm-softmmu/cpu-exec.o
CC alpha-softmmu/cpu-exec-common.o
CC cris-softmmu/tcg/tcg.o
CC alpha-softmmu/tcg/tcg.o
CC aarch64-softmmu/translate-common.o
CC arm-softmmu/translate-common.o
CC aarch64-softmmu/cpu-exec-common.o
CC arm-softmmu/cpu-exec-common.o
CC aarch64-softmmu/tcg/tcg.o
CC arm-softmmu/tcg/tcg.o
CC cris-softmmu/tcg/tcg-op.o
CC alpha-softmmu/tcg/tcg-op.o
CC arm-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/tcg-op.o
CC cris-softmmu/tcg/optimize.o
CC alpha-softmmu/tcg/optimize.o
CC cris-softmmu/tcg/tcg-common.o
CC cris-softmmu/fpu/softfloat.o
CC alpha-softmmu/tcg/tcg-common.o
CC alpha-softmmu/fpu/softfloat.o
CC arm-softmmu/tcg/optimize.o
CC aarch64-softmmu/tcg/optimize.o
CC arm-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/tcg/tcg-common.o
CC arm-softmmu/fpu/softfloat.o
CC aarch64-softmmu/fpu/softfloat.o
CC cris-softmmu/disas.o
CC alpha-softmmu/disas.o
CC cris-softmmu/tcg-runtime.o
CC alpha-softmmu/tcg-runtime.o
CC alpha-softmmu/hax-stub.o
CC cris-softmmu/hax-stub.o
CC alpha-softmmu/kvm-stub.o
CC cris-softmmu/kvm-stub.o
CC alpha-softmmu/arch_init.o
CC cris-softmmu/arch_init.o
CC arm-softmmu/disas.o
CC cris-softmmu/cpus.o
CC alpha-softmmu/cpus.o
CC arm-softmmu/tcg-runtime.o
CC cris-softmmu/monitor.o
GEN arm-softmmu/gdbstub-xml.c
CC alpha-softmmu/monitor.o
CC aarch64-softmmu/disas.o
CC aarch64-softmmu/tcg-runtime.o
CC arm-softmmu/hax-stub.o
GEN aarch64-softmmu/gdbstub-xml.c
CC arm-softmmu/kvm-stub.o
CC cris-softmmu/gdbstub.o
CC alpha-softmmu/gdbstub.o
CC arm-softmmu/arch_init.o
CC cris-softmmu/balloon.o
CC alpha-softmmu/balloon.o
CC arm-softmmu/cpus.o
CC cris-softmmu/ioport.o
CC aarch64-softmmu/hax-stub.o
CC alpha-softmmu/ioport.o
CC cris-softmmu/numa.o
CC aarch64-softmmu/kvm-stub.o
CC arm-softmmu/monitor.o
CC alpha-softmmu/numa.o
CC aarch64-softmmu/arch_init.o
CC cris-softmmu/qtest.o
CC aarch64-softmmu/cpus.o
CC alpha-softmmu/qtest.o
CC cris-softmmu/bootdevice.o
CC cris-softmmu/memory.o
CC alpha-softmmu/bootdevice.o
CC aarch64-softmmu/monitor.o
CC alpha-softmmu/memory.o
CC arm-softmmu/gdbstub.o
CC cris-softmmu/cputlb.o
CC arm-softmmu/balloon.o
CC alpha-softmmu/cputlb.o
CC arm-softmmu/ioport.o
CC aarch64-softmmu/gdbstub.o
CC arm-softmmu/numa.o
CC cris-softmmu/memory_mapping.o
CC cris-softmmu/dump.o
CC aarch64-softmmu/balloon.o
CC arm-softmmu/qtest.o
CC aarch64-softmmu/ioport.o
CC arm-softmmu/bootdevice.o
CC alpha-softmmu/memory_mapping.o
CC cris-softmmu/migration/ram.o
CC arm-softmmu/memory.o
CC alpha-softmmu/dump.o
CC aarch64-softmmu/numa.o
CC cris-softmmu/migration/savevm.o
CC aarch64-softmmu/qtest.o
CC alpha-softmmu/migration/ram.o
CC arm-softmmu/cputlb.o
CC aarch64-softmmu/bootdevice.o
CC cris-softmmu/xen-common-stub.o
CC aarch64-softmmu/memory.o
CC cris-softmmu/xen-hvm-stub.o
CC alpha-softmmu/migration/savevm.o
CC cris-softmmu/hw/core/nmi.o
CC cris-softmmu/hw/core/generic-loader.o
CC cris-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/cputlb.o
CC arm-softmmu/memory_mapping.o
CC cris-softmmu/hw/cpu/core.o
CC arm-softmmu/dump.o
CC cris-softmmu/hw/net/etraxfs_eth.o
CC alpha-softmmu/xen-common-stub.o
CC cris-softmmu/hw/net/vhost_net.o
CC alpha-softmmu/xen-hvm-stub.o
CC cris-softmmu/hw/net/rocker/qmp-norocker.o
CC cris-softmmu/hw/vfio/common.o
CC alpha-softmmu/hw/9pfs/virtio-9p-device.o
CC arm-softmmu/migration/ram.o
CC alpha-softmmu/hw/block/virtio-blk.o
CC aarch64-softmmu/memory_mapping.o
CC cris-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/dump.o
CC cris-softmmu/hw/vfio/spapr.o
CC arm-softmmu/migration/savevm.o
CC alpha-softmmu/hw/block/dataplane/virtio-blk.o
CC cris-softmmu/hw/cris/boot.o
CC aarch64-softmmu/migration/ram.o
CC alpha-softmmu/hw/char/virtio-serial-bus.o
CC cris-softmmu/hw/cris/axis_dev88.o
CC alpha-softmmu/hw/core/nmi.o
CC arm-softmmu/xen-common-stub.o
CC cris-softmmu/target/cris/translate.o
CC alpha-softmmu/hw/core/generic-loader.o
CC arm-softmmu/xen-hvm-stub.o
CC alpha-softmmu/hw/core/null-machine.o
CC arm-softmmu/hw/9pfs/virtio-9p-device.o
CC aarch64-softmmu/migration/savevm.o
CC arm-softmmu/hw/adc/stm32f2xx_adc.o
CC alpha-softmmu/hw/cpu/core.o
CC arm-softmmu/hw/block/virtio-blk.o
CC alpha-softmmu/hw/display/vga.o
CC aarch64-softmmu/xen-common-stub.o
CC arm-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/xen-hvm-stub.o
CC cris-softmmu/target/cris/op_helper.o
CC arm-softmmu/hw/char/exynos4210_uart.o
CC alpha-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/9pfs/virtio-9p-device.o
CC arm-softmmu/hw/char/omap_uart.o
CC arm-softmmu/hw/char/digic-uart.o
CC cris-softmmu/target/cris/helper.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC arm-softmmu/hw/char/stm32f2xx_usart.o
CC alpha-softmmu/hw/display/virtio-gpu-3d.o
CC cris-softmmu/target/cris/cpu.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC arm-softmmu/hw/char/bcm2835_aux.o
CC cris-softmmu/target/cris/gdbstub.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC alpha-softmmu/hw/display/virtio-gpu-pci.o
CC arm-softmmu/hw/char/virtio-serial-bus.o
CC cris-softmmu/target/cris/mmu.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC cris-softmmu/target/cris/machine.o
CC alpha-softmmu/hw/misc/ivshmem.o
CC arm-softmmu/hw/core/nmi.o
CC aarch64-softmmu/hw/char/omap_uart.o
GEN trace/generated-helpers.c
CC cris-softmmu/trace/control-target.o
CC arm-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC alpha-softmmu/hw/misc/edu.o
CC arm-softmmu/hw/core/null-machine.o
CC cris-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC alpha-softmmu/hw/net/virtio-net.o
LINK cris-softmmu/qemu-system-cris
CC arm-softmmu/hw/cpu/arm11mpcore.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC arm-softmmu/hw/cpu/realview_mpcore.o
CC arm-softmmu/hw/cpu/a9mpcore.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC alpha-softmmu/hw/net/vhost_net.o
CC arm-softmmu/hw/cpu/a15mpcore.o
CC alpha-softmmu/hw/scsi/virtio-scsi.o
CC arm-softmmu/hw/cpu/core.o
CC aarch64-softmmu/hw/core/nmi.o
CC arm-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC alpha-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC arm-softmmu/hw/display/omap_lcdc.o
CC alpha-softmmu/hw/scsi/vhost-scsi.o
CC arm-softmmu/hw/display/pxa2xx_lcd.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC alpha-softmmu/hw/timer/mc146818rtc.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC aarch64-softmmu/hw/cpu/core.o
CC alpha-softmmu/hw/vfio/common.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC arm-softmmu/hw/display/bcm2835_fb.o
GEN i386-softmmu/hmp-commands.h
GEN i386-softmmu/hmp-commands-info.h
CC aarch64-softmmu/hw/display/omap_lcdc.o
GEN i386-softmmu/config-target.h
CC i386-softmmu/exec.o
CC alpha-softmmu/hw/vfio/pci.o
CC arm-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC arm-softmmu/hw/display/virtio-gpu.o
CC alpha-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC i386-softmmu/translate-all.o
CC arm-softmmu/hw/display/virtio-gpu-3d.o
CC alpha-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/display/vga.o
CC i386-softmmu/cpu-exec.o
CC alpha-softmmu/hw/vfio/spapr.o
CC arm-softmmu/hw/display/virtio-gpu-pci.o
CC alpha-softmmu/hw/virtio/virtio.o
CC i386-softmmu/translate-common.o
CC arm-softmmu/hw/dma/omap_dma.o
CC i386-softmmu/cpu-exec-common.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC alpha-softmmu/hw/virtio/virtio-balloon.o
CC i386-softmmu/tcg/tcg.o
CC arm-softmmu/hw/dma/soc_dma.o
CC alpha-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC arm-softmmu/hw/dma/pxa2xx_dma.o
CC arm-softmmu/hw/dma/bcm2835_dma.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC alpha-softmmu/hw/virtio/vhost-backend.o
CC arm-softmmu/hw/gpio/omap_gpio.o
CC aarch64-softmmu/hw/display/dpcd.o
CC alpha-softmmu/hw/virtio/vhost-user.o
CC arm-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC alpha-softmmu/hw/virtio/vhost-vsock.o
CC i386-softmmu/tcg/tcg-op.o
CC arm-softmmu/hw/gpio/bcm2835_gpio.o
CC alpha-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC arm-softmmu/hw/i2c/omap_i2c.o
CC alpha-softmmu/hw/virtio/virtio-crypto-pci.o
CC alpha-softmmu/hw/alpha/dp264.o
CC arm-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC alpha-softmmu/hw/alpha/pci.o
CC arm-softmmu/hw/input/tsc210x.o
CC alpha-softmmu/hw/alpha/typhoon.o
CC aarch64-softmmu/hw/dma/soc_dma.o
CC alpha-softmmu/target/alpha/machine.o
CC arm-softmmu/hw/intc/armv7m_nvic.o
CC alpha-softmmu/target/alpha/translate.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC i386-softmmu/tcg/optimize.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC arm-softmmu/hw/intc/exynos4210_gic.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC arm-softmmu/hw/intc/exynos4210_combiner.o
CC alpha-softmmu/target/alpha/helper.o
CC arm-softmmu/hw/intc/omap_intc.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC alpha-softmmu/target/alpha/cpu.o
CC i386-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
CC alpha-softmmu/target/alpha/int_helper.o
CC i386-softmmu/fpu/softfloat.o
CC arm-softmmu/hw/intc/bcm2835_ic.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC alpha-softmmu/target/alpha/fpu_helper.o
CC arm-softmmu/hw/intc/bcm2836_control.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC arm-softmmu/hw/intc/allwinner-a10-pic.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC alpha-softmmu/target/alpha/vax_helper.o
CC arm-softmmu/hw/intc/aspeed_vic.o
CC alpha-softmmu/target/alpha/sys_helper.o
CC arm-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC alpha-softmmu/target/alpha/mem_helper.o
CC alpha-softmmu/target/alpha/gdbstub.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC arm-softmmu/hw/misc/ivshmem.o
CC i386-softmmu/disas.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC alpha-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC alpha-softmmu/trace/generated-helpers.o
CC i386-softmmu/tcg-runtime.o
CC arm-softmmu/hw/misc/arm_sysctl.o
LINK alpha-softmmu/qemu-system-alpha
CC i386-softmmu/hax-stub.o
CC arm-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC i386-softmmu/kvm-stub.o
CC i386-softmmu/arch_init.o
CC arm-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC i386-softmmu/cpus.o
CC arm-softmmu/hw/misc/exynos4210_clk.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC i386-softmmu/monitor.o
CC arm-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC arm-softmmu/hw/misc/imx31_ccm.o
CC arm-softmmu/hw/misc/imx25_ccm.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC arm-softmmu/hw/misc/imx6_ccm.o
CC arm-softmmu/hw/misc/imx6_src.o
CC arm-softmmu/hw/misc/mst_fpga.o
CC i386-softmmu/gdbstub.o
CC arm-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/ivshmem.o
GEN lm32-softmmu/hmp-commands.h
GEN lm32-softmmu/hmp-commands-info.h
GEN lm32-softmmu/config-target.h
CC arm-softmmu/hw/misc/omap_gpmc.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC lm32-softmmu/exec.o
CC i386-softmmu/balloon.o
CC arm-softmmu/hw/misc/omap_l4.o
CC aarch64-softmmu/hw/misc/cbus.o
CC i386-softmmu/ioport.o
CC arm-softmmu/hw/misc/omap_sdrc.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC i386-softmmu/numa.o
CC arm-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/exynos4210_clk.o
CC arm-softmmu/hw/misc/bcm2835_mbox.o
CC i386-softmmu/qtest.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC arm-softmmu/hw/misc/bcm2835_property.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC lm32-softmmu/translate-all.o
CC i386-softmmu/bootdevice.o
CC arm-softmmu/hw/misc/bcm2835_rng.o
CC i386-softmmu/memory.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC arm-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC lm32-softmmu/cpu-exec.o
CC arm-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC arm-softmmu/hw/misc/stm32f2xx_syscfg.o
CC lm32-softmmu/translate-common.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC i386-softmmu/cputlb.o
CC arm-softmmu/hw/misc/edu.o
CC lm32-softmmu/cpu-exec-common.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC lm32-softmmu/tcg/tcg.o
CC arm-softmmu/hw/misc/aspeed_scu.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC arm-softmmu/hw/misc/aspeed_sdmc.o
CC i386-softmmu/memory_mapping.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
CC arm-softmmu/hw/net/virtio-net.o
CC i386-softmmu/dump.o
CC aarch64-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC lm32-softmmu/tcg/tcg-op.o
CC i386-softmmu/migration/ram.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC arm-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/misc/bcm2835_rng.o
CC arm-softmmu/hw/pcmcia/pxa2xx.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC arm-softmmu/hw/scsi/virtio-scsi.o
CC i386-softmmu/migration/savevm.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC arm-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC aarch64-softmmu/hw/misc/edu.o
CC arm-softmmu/hw/scsi/vhost-scsi.o
CC i386-softmmu/xen-common-stub.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC lm32-softmmu/tcg/optimize.o
CC arm-softmmu/hw/sd/omap_mmc.o
CC i386-softmmu/xen-hvm-stub.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC arm-softmmu/hw/sd/pxa2xx_mmci.o
CC i386-softmmu/hw/9pfs/virtio-9p-device.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC lm32-softmmu/tcg/tcg-common.o
CC i386-softmmu/hw/block/virtio-blk.o
CC arm-softmmu/hw/sd/bcm2835_sdhost.o
CC lm32-softmmu/fpu/softfloat.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC arm-softmmu/hw/ssi/omap_spi.o
CC i386-softmmu/hw/block/dataplane/virtio-blk.o
CC arm-softmmu/hw/ssi/imx_spi.o
CC i386-softmmu/hw/char/virtio-serial-bus.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC arm-softmmu/hw/timer/exynos4210_mct.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC arm-softmmu/hw/timer/exynos4210_pwm.o
CC i386-softmmu/hw/core/nmi.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC arm-softmmu/hw/timer/exynos4210_rtc.o
CC i386-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC i386-softmmu/hw/core/null-machine.o
CC arm-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/scsi/vhost-scsi.o
CC i386-softmmu/hw/cpu/core.o
CC arm-softmmu/hw/timer/omap_synctimer.o
CC lm32-softmmu/disas.o
CC i386-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC arm-softmmu/hw/timer/pxa2xx_timer.o
CC lm32-softmmu/tcg-runtime.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC arm-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/sd/bcm2835_sdhost.o
CC lm32-softmmu/hax-stub.o
CC arm-softmmu/hw/timer/allwinner-a10-pit.o
CC i386-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC arm-softmmu/hw/usb/tusb6010.o
CC lm32-softmmu/kvm-stub.o
CC lm32-softmmu/arch_init.o
CC arm-softmmu/hw/vfio/common.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC lm32-softmmu/cpus.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC i386-softmmu/hw/display/virtio-gpu-3d.o
CC arm-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC i386-softmmu/hw/display/virtio-gpu-pci.o
CC lm32-softmmu/monitor.o
CC i386-softmmu/hw/display/virtio-vga.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC arm-softmmu/hw/vfio/pci-quirks.o
CC i386-softmmu/hw/intc/apic.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC lm32-softmmu/gdbstub.o
CC i386-softmmu/hw/intc/apic_common.o
CC arm-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC i386-softmmu/hw/intc/ioapic.o
CC arm-softmmu/hw/vfio/calxeda-xgmac.o
CC lm32-softmmu/balloon.o
CC arm-softmmu/hw/vfio/amd-xgbe.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC lm32-softmmu/ioport.o
CC i386-softmmu/hw/isa/lpc_ich9.o
CC arm-softmmu/hw/vfio/spapr.o
CC aarch64-softmmu/hw/vfio/common.o
CC lm32-softmmu/numa.o
CC i386-softmmu/hw/misc/vmport.o
CC arm-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/vfio/pci.o
CC i386-softmmu/hw/misc/ivshmem.o
CC lm32-softmmu/qtest.o
CC i386-softmmu/hw/misc/pvpanic.o
CC arm-softmmu/hw/virtio/virtio-balloon.o
CC i386-softmmu/hw/misc/edu.o
CC lm32-softmmu/bootdevice.o
CC arm-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/vfio/pci-quirks.o
CC lm32-softmmu/memory.o
CC i386-softmmu/hw/net/virtio-net.o
CC arm-softmmu/hw/virtio/vhost-backend.o
CC aarch64-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/vfio/calxeda-xgmac.o
CC arm-softmmu/hw/virtio/vhost-user.o
CC aarch64-softmmu/hw/vfio/amd-xgbe.o
CC i386-softmmu/hw/net/vhost_net.o
CC arm-softmmu/hw/virtio/vhost-vsock.o
CC aarch64-softmmu/hw/vfio/spapr.o
CC i386-softmmu/hw/scsi/virtio-scsi.o
CC lm32-softmmu/cputlb.o
CC arm-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC arm-softmmu/hw/virtio/virtio-crypto-pci.o
CC i386-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC arm-softmmu/hw/arm/boot.o
CC i386-softmmu/hw/scsi/vhost-scsi.o
CC arm-softmmu/hw/arm/collie.o
CC i386-softmmu/hw/timer/mc146818rtc.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
CC lm32-softmmu/memory_mapping.o
CC lm32-softmmu/dump.o
CC arm-softmmu/hw/arm/exynos4_boards.o
CC aarch64-softmmu/hw/virtio/vhost.o
CC i386-softmmu/hw/vfio/common.o
CC arm-softmmu/hw/arm/gumstix.o
CC arm-softmmu/hw/arm/highbank.o
CC lm32-softmmu/migration/ram.o
CC i386-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/virtio/vhost-backend.o
CC arm-softmmu/hw/arm/digic_boards.o
CC i386-softmmu/hw/vfio/pci-quirks.o
CC arm-softmmu/hw/arm/integratorcp.o
CC aarch64-softmmu/hw/virtio/vhost-user.o
CC lm32-softmmu/migration/savevm.o
CC aarch64-softmmu/hw/virtio/vhost-vsock.o
CC i386-softmmu/hw/vfio/platform.o
CC arm-softmmu/hw/arm/mainstone.o
CC aarch64-softmmu/hw/virtio/virtio-crypto.o
CC arm-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o
CC i386-softmmu/hw/vfio/spapr.o
CC lm32-softmmu/xen-common-stub.o
CC aarch64-softmmu/hw/arm/boot.o
CC lm32-softmmu/xen-hvm-stub.o
CC i386-softmmu/hw/virtio/virtio.o
CC lm32-softmmu/hw/core/nmi.o
CC arm-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/collie.o
CC lm32-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
CC lm32-softmmu/hw/core/null-machine.o
CC arm-softmmu/hw/arm/omap_sx1.o
CC i386-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/arm/gumstix.o
CC lm32-softmmu/hw/cpu/core.o
CC aarch64-softmmu/hw/arm/highbank.o
CC i386-softmmu/hw/virtio/vhost.o
CC arm-softmmu/hw/arm/palm.o
CC lm32-softmmu/hw/input/milkymist-softusb.o
CC arm-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC i386-softmmu/hw/virtio/vhost-backend.o
CC arm-softmmu/hw/arm/spitz.o
CC lm32-softmmu/hw/misc/milkymist-hpdmc.o
CC aarch64-softmmu/hw/arm/integratorcp.o
CC i386-softmmu/hw/virtio/vhost-user.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC lm32-softmmu/hw/misc/milkymist-pfpu.o
CC arm-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC i386-softmmu/hw/virtio/vhost-vsock.o
CC lm32-softmmu/hw/net/milkymist-minimac2.o
CC i386-softmmu/hw/virtio/virtio-crypto.o
CC arm-softmmu/hw/arm/tosa.o
CC lm32-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/arm/nseries.o
CC lm32-softmmu/hw/net/rocker/qmp-norocker.o
CC arm-softmmu/hw/arm/versatilepb.o
CC i386-softmmu/hw/virtio/virtio-crypto-pci.o
CC lm32-softmmu/hw/sd/milkymist-memcard.o
CC arm-softmmu/hw/arm/vexpress.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC i386-softmmu/hw/i386/multiboot.o
CC lm32-softmmu/hw/vfio/common.o
CC arm-softmmu/hw/arm/virt.o
CC i386-softmmu/hw/i386/pc.o
CC aarch64-softmmu/hw/arm/palm.o
CC lm32-softmmu/hw/vfio/platform.o
CC arm-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/realview.o
CC arm-softmmu/hw/arm/z2.o
CC lm32-softmmu/hw/vfio/spapr.o
CC i386-softmmu/hw/i386/pc_piix.o
CC aarch64-softmmu/hw/arm/spitz.o
CC lm32-softmmu/hw/lm32/lm32_boards.o
CC arm-softmmu/hw/arm/virt-acpi-build.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC i386-softmmu/hw/i386/pc_q35.o
CC lm32-softmmu/hw/lm32/milkymist.o
CC arm-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/tosa.o
CC arm-softmmu/hw/arm/sysbus-fdt.o
CC i386-softmmu/hw/i386/pc_sysfw.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC lm32-softmmu/target/lm32/translate.o
CC arm-softmmu/hw/arm/armv7m.o
CC i386-softmmu/hw/i386/x86-iommu.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC i386-softmmu/hw/i386/intel_iommu.o
CC arm-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/virt.o
CC lm32-softmmu/target/lm32/op_helper.o
CC arm-softmmu/hw/arm/pxa2xx.o
CC lm32-softmmu/target/lm32/helper.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC lm32-softmmu/target/lm32/cpu.o
CC i386-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/arm/z2.o
CC lm32-softmmu/target/lm32/gdbstub.o
CC lm32-softmmu/target/lm32/lm32-semi.o
CC arm-softmmu/hw/arm/pxa2xx_gpio.o
CC i386-softmmu/hw/i386/kvmvapic.o
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC lm32-softmmu/target/lm32/machine.o
CC arm-softmmu/hw/arm/pxa2xx_pic.o
CC i386-softmmu/hw/i386/acpi-build.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/hw/arm/netduino2.o
CC lm32-softmmu/trace/control-target.o
CC arm-softmmu/hw/arm/digic.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC lm32-softmmu/trace/generated-helpers.o
CC arm-softmmu/hw/arm/omap1.o
LINK lm32-softmmu/qemu-system-lm32
CC aarch64-softmmu/hw/arm/armv7m.o
CC i386-softmmu/hw/i386/pci-assign-load-rom.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC arm-softmmu/hw/arm/omap2.o
CC i386-softmmu/target/i386/translate.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC arm-softmmu/hw/arm/strongarm.o
GEN m68k-softmmu/hmp-commands.h
GEN m68k-softmmu/hmp-commands-info.h
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
GEN m68k-softmmu/config-target.h
CC m68k-softmmu/exec.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC arm-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/digic.o
CC arm-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/omap1.o
CC arm-softmmu/hw/arm/bcm2835_peripherals.o
CC arm-softmmu/hw/arm/bcm2836.o
CC m68k-softmmu/translate-all.o
CC arm-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/omap2.o
CC m68k-softmmu/cpu-exec.o
CC arm-softmmu/hw/arm/stm32f205_soc.o
CC m68k-softmmu/translate-common.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC arm-softmmu/hw/arm/fsl-imx25.o
CC m68k-softmmu/cpu-exec-common.o
CC arm-softmmu/hw/arm/imx25_pdk.o
CC m68k-softmmu/tcg/tcg.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC arm-softmmu/hw/arm/fsl-imx31.o
CC arm-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC arm-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC i386-softmmu/target/i386/helper.o
CC arm-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC m68k-softmmu/tcg/tcg-op.o
CC i386-softmmu/target/i386/cpu.o
CC arm-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/hw/arm/raspi.o
CC arm-softmmu/hw/arm/aspeed.o
CC i386-softmmu/target/i386/bpt_helper.o
CC arm-softmmu/target/arm/arm-semi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC i386-softmmu/target/i386/excp_helper.o
CC arm-softmmu/target/arm/machine.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC arm-softmmu/target/arm/psci.o
CC i386-softmmu/target/i386/fpu_helper.o
CC aarch64-softmmu/hw/arm/xlnx-ep108.o
CC arm-softmmu/target/arm/arch_dump.o
CC m68k-softmmu/tcg/optimize.o
CC arm-softmmu/target/arm/monitor.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC arm-softmmu/target/arm/kvm-stub.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC arm-softmmu/target/arm/translate.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
CC m68k-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/hw/arm/kzm.o
CC m68k-softmmu/fpu/softfloat.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC i386-softmmu/target/i386/cc_helper.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC i386-softmmu/target/i386/int_helper.o
CC aarch64-softmmu/target/arm/arm-semi.o
CC i386-softmmu/target/i386/svm_helper.o
CC aarch64-softmmu/target/arm/machine.o
CC m68k-softmmu/disas.o
CC i386-softmmu/target/i386/smm_helper.o
CC aarch64-softmmu/target/arm/psci.o
CC m68k-softmmu/tcg-runtime.o
CC i386-softmmu/target/i386/misc_helper.o
GEN m68k-softmmu/gdbstub-xml.c
CC aarch64-softmmu/target/arm/arch_dump.o
CC i386-softmmu/target/i386/mem_helper.o
CC m68k-softmmu/hax-stub.o
CC aarch64-softmmu/target/arm/monitor.o
CC m68k-softmmu/kvm-stub.o
CC i386-softmmu/target/i386/seg_helper.o
CC aarch64-softmmu/target/arm/kvm-stub.o
CC m68k-softmmu/arch_init.o
CC aarch64-softmmu/target/arm/translate.o
CC m68k-softmmu/cpus.o
CC arm-softmmu/target/arm/op_helper.o
CC m68k-softmmu/monitor.o
CC arm-softmmu/target/arm/helper.o
CC i386-softmmu/target/i386/mpx_helper.o
CC m68k-softmmu/gdbstub.o
CC i386-softmmu/target/i386/gdbstub.o
CC i386-softmmu/target/i386/machine.o
CC m68k-softmmu/balloon.o
CC m68k-softmmu/ioport.o
CC i386-softmmu/target/i386/arch_memory_mapping.o
CC m68k-softmmu/numa.o
CC i386-softmmu/target/i386/arch_dump.o
CC m68k-softmmu/qtest.o
CC i386-softmmu/target/i386/monitor.o
CC arm-softmmu/target/arm/cpu.o
CC m68k-softmmu/bootdevice.o
CC i386-softmmu/target/i386/kvm-stub.o
CC arm-softmmu/target/arm/neon_helper.o
CC m68k-softmmu/memory.o
GEN trace/generated-helpers.c
CC i386-softmmu/trace/control-target.o
CC aarch64-softmmu/target/arm/op_helper.o
CC i386-softmmu/trace/generated-helpers.o
LINK i386-softmmu/qemu-system-i386
CC arm-softmmu/target/arm/iwmmxt_helper.o
CC m68k-softmmu/cputlb.o
CC aarch64-softmmu/target/arm/helper.o
CC arm-softmmu/target/arm/gdbstub.o
CC arm-softmmu/target/arm/crypto_helper.o
CC m68k-softmmu/memory_mapping.o
GEN microblazeel-softmmu/hmp-commands.h
GEN microblazeel-softmmu/hmp-commands-info.h
CC arm-softmmu/target/arm/arm-powerctl.o
GEN microblazeel-softmmu/config-target.h
CC microblazeel-softmmu/exec.o
CC m68k-softmmu/dump.o
GEN trace/generated-helpers.c
CC arm-softmmu/trace/control-target.o
CC arm-softmmu/gdbstub-xml.o
CC m68k-softmmu/migration/ram.o
CC arm-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/target/arm/cpu.o
CC m68k-softmmu/migration/savevm.o
LINK arm-softmmu/qemu-system-arm
CC microblazeel-softmmu/translate-all.o
CC aarch64-softmmu/target/arm/neon_helper.o
CC microblazeel-softmmu/cpu-exec.o
CC m68k-softmmu/xen-common-stub.o
CC microblazeel-softmmu/translate-common.o
CC m68k-softmmu/xen-hvm-stub.o
CC m68k-softmmu/hw/char/mcf_uart.o
CC microblazeel-softmmu/cpu-exec-common.o
CC aarch64-softmmu/target/arm/iwmmxt_helper.o
CC microblazeel-softmmu/tcg/tcg.o
CC m68k-softmmu/hw/core/nmi.o
CC m68k-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/target/arm/gdbstub.o
CC m68k-softmmu/hw/core/null-machine.o
GEN microblaze-softmmu/hmp-commands.h
CC m68k-softmmu/hw/cpu/core.o
GEN microblaze-softmmu/hmp-commands-info.h
CC aarch64-softmmu/target/arm/cpu64.o
GEN microblaze-softmmu/config-target.h
CC microblaze-softmmu/exec.o
CC m68k-softmmu/hw/net/mcf_fec.o
CC aarch64-softmmu/target/arm/translate-a64.o
CC m68k-softmmu/hw/net/vhost_net.o
CC microblazeel-softmmu/tcg/tcg-op.o
CC m68k-softmmu/hw/net/rocker/qmp-norocker.o
CC m68k-softmmu/hw/vfio/common.o
CC microblaze-softmmu/translate-all.o
CC m68k-softmmu/hw/vfio/platform.o
CC microblazeel-softmmu/tcg/optimize.o
CC m68k-softmmu/hw/vfio/spapr.o
CC microblaze-softmmu/cpu-exec.o
CC m68k-softmmu/hw/m68k/an5206.o
CC microblaze-softmmu/translate-common.o
CC m68k-softmmu/hw/m68k/mcf5208.o
CC microblaze-softmmu/cpu-exec-common.o
CC microblaze-softmmu/tcg/tcg.o
CC m68k-softmmu/hw/m68k/mcf5206.o
CC microblazeel-softmmu/tcg/tcg-common.o
CC microblazeel-softmmu/fpu/softfloat.o
CC m68k-softmmu/hw/m68k/mcf_intc.o
CC aarch64-softmmu/target/arm/helper-a64.o
CC m68k-softmmu/target/m68k/m68k-semi.o
CC aarch64-softmmu/target/arm/gdbstub64.o
CC m68k-softmmu/target/m68k/translate.o
CC aarch64-softmmu/target/arm/crypto_helper.o
CC microblaze-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/target/arm/arm-powerctl.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/trace/control-target.o
CC aarch64-softmmu/gdbstub-xml.o
CC microblazeel-softmmu/disas.o
CC aarch64-softmmu/trace/generated-helpers.o
CC m68k-softmmu/target/m68k/op_helper.o
CC microblazeel-softmmu/tcg-runtime.o
LINK aarch64-softmmu/qemu-system-aarch64
CC microblazeel-softmmu/hax-stub.o
CC microblaze-softmmu/tcg/optimize.o
CC m68k-softmmu/target/m68k/helper.o
CC microblazeel-softmmu/kvm-stub.o
CC microblazeel-softmmu/arch_init.o
CC m68k-softmmu/target/m68k/cpu.o
CC microblazeel-softmmu/cpus.o
CC microblaze-softmmu/tcg/tcg-common.o
CC m68k-softmmu/target/m68k/gdbstub.o
CC microblaze-softmmu/fpu/softfloat.o
GEN trace/generated-helpers.c
CC m68k-softmmu/trace/control-target.o
CC microblazeel-softmmu/monitor.o
CC m68k-softmmu/gdbstub-xml.o
CC m68k-softmmu/trace/generated-helpers.o
LINK m68k-softmmu/qemu-system-m68k
GEN mips64el-softmmu/hmp-commands.h
CC microblazeel-softmmu/gdbstub.o
GEN mips64el-softmmu/hmp-commands-info.h
GEN mips64el-softmmu/config-target.h
CC mips64el-softmmu/exec.o
CC microblazeel-softmmu/balloon.o
CC microblazeel-softmmu/ioport.o
CC microblaze-softmmu/disas.o
CC microblazeel-softmmu/numa.o
CC microblaze-softmmu/tcg-runtime.o
CC microblazeel-softmmu/qtest.o
CC microblaze-softmmu/hax-stub.o
CC mips64el-softmmu/translate-all.o
CC microblaze-softmmu/kvm-stub.o
CC microblazeel-softmmu/bootdevice.o
CC microblaze-softmmu/arch_init.o
CC microblazeel-softmmu/memory.o
CC mips64el-softmmu/cpu-exec.o
CC microblaze-softmmu/cpus.o
CC mips64el-softmmu/translate-common.o
CC mips64el-softmmu/cpu-exec-common.o
GEN mips64-softmmu/hmp-commands.h
GEN mips64-softmmu/hmp-commands-info.h
GEN mips64-softmmu/config-target.h
CC mips64-softmmu/exec.o
CC microblaze-softmmu/monitor.o
CC mips64el-softmmu/tcg/tcg.o
CC microblazeel-softmmu/cputlb.o
CC microblaze-softmmu/gdbstub.o
CC mips64-softmmu/translate-all.o
CC microblazeel-softmmu/memory_mapping.o
CC microblaze-softmmu/balloon.o
CC mips64el-softmmu/tcg/tcg-op.o
CC microblazeel-softmmu/dump.o
CC mips64-softmmu/cpu-exec.o
CC microblaze-softmmu/ioport.o
CC mips64-softmmu/translate-common.o
CC microblaze-softmmu/numa.o
CC microblazeel-softmmu/migration/ram.o
CC mips64-softmmu/cpu-exec-common.o
CC microblaze-softmmu/qtest.o
CC mips64-softmmu/tcg/tcg.o
CC microblaze-softmmu/bootdevice.o
CC microblaze-softmmu/memory.o
CC microblazeel-softmmu/migration/savevm.o
CC mips64el-softmmu/tcg/optimize.o
CC microblazeel-softmmu/xen-common-stub.o
CC microblaze-softmmu/cputlb.o
CC microblazeel-softmmu/xen-hvm-stub.o
CC mips64-softmmu/tcg/tcg-op.o
CC microblazeel-softmmu/hw/core/nmi.o
CC microblazeel-softmmu/hw/core/generic-loader.o
CC microblazeel-softmmu/hw/core/null-machine.o
CC mips64el-softmmu/tcg/tcg-common.o
CC microblazeel-softmmu/hw/cpu/core.o
CC mips64el-softmmu/fpu/softfloat.o
CC microblazeel-softmmu/hw/net/xilinx_ethlite.o
CC microblaze-softmmu/memory_mapping.o
CC microblaze-softmmu/dump.o
CC microblazeel-softmmu/hw/net/vhost_net.o
CC microblazeel-softmmu/hw/net/rocker/qmp-norocker.o
CC microblaze-softmmu/migration/ram.o
CC microblazeel-softmmu/hw/vfio/common.o
CC mips64-softmmu/tcg/optimize.o
CC microblazeel-softmmu/hw/vfio/platform.o
CC microblaze-softmmu/migration/savevm.o
CC microblazeel-softmmu/hw/vfio/spapr.o
CC mips64el-softmmu/disas.o
CC microblazeel-softmmu/hw/microblaze/petalogix_s3adsp1800_mmu.o
CC mips64-softmmu/tcg/tcg-common.o
CC mips64el-softmmu/tcg-runtime.o
CC microblaze-softmmu/xen-common-stub.o
CC microblazeel-softmmu/hw/microblaze/petalogix_ml605_mmu.o
CC mips64-softmmu/fpu/softfloat.o
CC microblaze-softmmu/xen-hvm-stub.o
CC mips64el-softmmu/hax-stub.o
CC microblaze-softmmu/hw/core/nmi.o
CC microblazeel-softmmu/hw/microblaze/boot.o
CC microblaze-softmmu/hw/core/generic-loader.o
CC mips64el-softmmu/kvm-stub.o
CC microblazeel-softmmu/target/microblaze/translate.o
CC microblaze-softmmu/hw/core/null-machine.o
CC mips64el-softmmu/arch_init.o
CC microblaze-softmmu/hw/cpu/core.o
CC mips64el-softmmu/cpus.o
CC microblaze-softmmu/hw/net/xilinx_ethlite.o
CC microblazeel-softmmu/target/microblaze/op_helper.o
CC microblaze-softmmu/hw/net/vhost_net.o
CC mips64el-softmmu/monitor.o
CC microblaze-softmmu/hw/net/rocker/qmp-norocker.o
CC microblazeel-softmmu/target/microblaze/helper.o
CC microblaze-softmmu/hw/vfio/common.o
CC mips64-softmmu/disas.o
CC microblazeel-softmmu/target/microblaze/cpu.o
CC mips64-softmmu/tcg-runtime.o
CC microblazeel-softmmu/target/microblaze/gdbstub.o
CC microblaze-softmmu/hw/vfio/platform.o
CC mips64-softmmu/hax-stub.o
CC mips64el-softmmu/gdbstub.o
CC microblazeel-softmmu/target/microblaze/mmu.o
CC mips64-softmmu/kvm-stub.o
CC microblaze-softmmu/hw/vfio/spapr.o
GEN trace/generated-helpers.c
CC microblazeel-softmmu/trace/control-target.o
CC mips64el-softmmu/balloon.o
CC microblaze-softmmu/hw/microblaze/petalogix_s3adsp1800_mmu.o
CC mips64-softmmu/arch_init.o
CC microblazeel-softmmu/trace/generated-helpers.o
CC mips64el-softmmu/ioport.o
CC microblaze-softmmu/hw/microblaze/petalogix_ml605_mmu.o
CC mips64-softmmu/cpus.o
LINK microblazeel-softmmu/qemu-system-microblazeel
CC microblaze-softmmu/hw/microblaze/boot.o
CC mips64el-softmmu/numa.o
CC microblaze-softmmu/target/microblaze/translate.o
CC mips64-softmmu/monitor.o
CC mips64el-softmmu/qtest.o
CC mips64el-softmmu/bootdevice.o
CC microblaze-softmmu/target/microblaze/op_helper.o
CC microblaze-softmmu/target/microblaze/helper.o
CC mips64el-softmmu/memory.o
CC microblaze-softmmu/target/microblaze/cpu.o
CC microblaze-softmmu/target/microblaze/gdbstub.o
CC mips64-softmmu/gdbstub.o
CC microblaze-softmmu/target/microblaze/mmu.o
CC mips64el-softmmu/cputlb.o
GEN mipsel-softmmu/hmp-commands.h
GEN trace/generated-helpers.c
CC microblaze-softmmu/trace/control-target.o
GEN mipsel-softmmu/hmp-commands-info.h
GEN mipsel-softmmu/config-target.h
CC mips64-softmmu/balloon.o
CC mipsel-softmmu/exec.o
CC mips64-softmmu/ioport.o
CC microblaze-softmmu/trace/generated-helpers.o
LINK microblaze-softmmu/qemu-system-microblaze
CC mips64-softmmu/numa.o
CC mips64el-softmmu/memory_mapping.o
CC mips64-softmmu/qtest.o
CC mips64el-softmmu/dump.o
CC mips64-softmmu/bootdevice.o
CC mips64el-softmmu/migration/ram.o
CC mips64-softmmu/memory.o
CC mips64el-softmmu/migration/savevm.o
CC mipsel-softmmu/translate-all.o
CC mipsel-softmmu/cpu-exec.o
CC mips64-softmmu/cputlb.o
CC mips64el-softmmu/xen-common-stub.o
CC mipsel-softmmu/translate-common.o
CC mips64el-softmmu/xen-hvm-stub.o
GEN mips-softmmu/hmp-commands.h
CC mipsel-softmmu/cpu-exec-common.o
CC mips64el-softmmu/hw/9pfs/virtio-9p-device.o
GEN mips-softmmu/hmp-commands-info.h
GEN mips-softmmu/config-target.h
CC mips-softmmu/exec.o
CC mips64el-softmmu/hw/block/virtio-blk.o
CC mipsel-softmmu/tcg/tcg.o
CC mips64-softmmu/memory_mapping.o
CC mips64el-softmmu/hw/block/dataplane/virtio-blk.o
CC mips64-softmmu/dump.o
CC mips64el-softmmu/hw/char/virtio-serial-bus.o
CC mips64-softmmu/migration/ram.o
CC mips64el-softmmu/hw/core/nmi.o
CC mips-softmmu/translate-all.o
CC mips64el-softmmu/hw/core/generic-loader.o
CC mipsel-softmmu/tcg/tcg-op.o
CC mips64-softmmu/migration/savevm.o
CC mips64el-softmmu/hw/core/null-machine.o
CC mips64el-softmmu/hw/cpu/core.o
CC mips-softmmu/cpu-exec.o
CC mips64el-softmmu/hw/display/vga.o
CC mips-softmmu/translate-common.o
CC mips64-softmmu/xen-common-stub.o
CC mips-softmmu/cpu-exec-common.o
CC mips64-softmmu/xen-hvm-stub.o
CC mips-softmmu/tcg/tcg.o
CC mips64el-softmmu/hw/display/virtio-gpu.o
CC mips64-softmmu/hw/9pfs/virtio-9p-device.o
CC mips64-softmmu/hw/block/virtio-blk.o
CC mipsel-softmmu/tcg/optimize.o
CC mips64-softmmu/hw/block/dataplane/virtio-blk.o
CC mips64el-softmmu/hw/display/virtio-gpu-3d.o
CC mips64-softmmu/hw/char/virtio-serial-bus.o
CC mips64-softmmu/hw/core/nmi.o
CC mips64el-softmmu/hw/display/virtio-gpu-pci.o
CC mipsel-softmmu/tcg/tcg-common.o
CC mips-softmmu/tcg/tcg-op.o
CC mips64-softmmu/hw/core/generic-loader.o
CC mipsel-softmmu/fpu/softfloat.o
CC mips64-softmmu/hw/core/null-machine.o
CC mips64el-softmmu/hw/intc/mips_gic.o
CC mips64-softmmu/hw/cpu/core.o
CC mips64el-softmmu/hw/misc/ivshmem.o
CC mips64-softmmu/hw/display/vga.o
CC mips64el-softmmu/hw/misc/mips_cmgcr.o
CC mips64el-softmmu/hw/misc/mips_cpc.o
CC mips64-softmmu/hw/display/virtio-gpu.o
CC mips64el-softmmu/hw/misc/mips_itu.o
CC mips-softmmu/tcg/optimize.o
CC mipsel-softmmu/disas.o
CC mips64el-softmmu/hw/misc/edu.o
CC mipsel-softmmu/tcg-runtime.o
CC mips64-softmmu/hw/display/virtio-gpu-3d.o
CC mips64el-softmmu/hw/net/virtio-net.o
CC mipsel-softmmu/hax-stub.o
CC mips-softmmu/tcg/tcg-common.o
CC mipsel-softmmu/kvm-stub.o
CC mips-softmmu/fpu/softfloat.o
CC mips64el-softmmu/hw/net/vhost_net.o
CC mips64-softmmu/hw/display/virtio-gpu-pci.o
CC mipsel-softmmu/arch_init.o
CC mips64el-softmmu/hw/scsi/virtio-scsi.o
CC mips64-softmmu/hw/intc/mips_gic.o
CC mips64-softmmu/hw/misc/ivshmem.o
CC mipsel-softmmu/cpus.o
CC mips64el-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC mips64el-softmmu/hw/scsi/vhost-scsi.o
CC mips64-softmmu/hw/misc/mips_cmgcr.o
CC mipsel-softmmu/monitor.o
CC mips64el-softmmu/hw/timer/mips_gictimer.o
CC mips64el-softmmu/hw/timer/mc146818rtc.o
CC mips64-softmmu/hw/misc/mips_cpc.o
CC mips64-softmmu/hw/misc/mips_itu.o
CC mips64el-softmmu/hw/vfio/common.o
CC mips-softmmu/disas.o
CC mips64-softmmu/hw/misc/edu.o
CC mipsel-softmmu/gdbstub.o
CC mips-softmmu/tcg-runtime.o
CC mips64-softmmu/hw/net/virtio-net.o
CC mips64el-softmmu/hw/vfio/pci.o
CC mips-softmmu/hax-stub.o
CC mipsel-softmmu/balloon.o
CC mips-softmmu/kvm-stub.o
CC mips64-softmmu/hw/net/vhost_net.o
CC mipsel-softmmu/ioport.o
CC mips-softmmu/arch_init.o
CC mips64el-softmmu/hw/vfio/pci-quirks.o
CC mips64-softmmu/hw/scsi/virtio-scsi.o
CC mipsel-softmmu/numa.o
CC mips-softmmu/cpus.o
CC mipsel-softmmu/qtest.o
CC mips64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC mips64el-softmmu/hw/vfio/platform.o
CC mips-softmmu/monitor.o
CC mips64-softmmu/hw/scsi/vhost-scsi.o
CC mips64el-softmmu/hw/vfio/spapr.o
CC mipsel-softmmu/bootdevice.o
CC mips64-softmmu/hw/timer/mips_gictimer.o
CC mipsel-softmmu/memory.o
CC mips64el-softmmu/hw/virtio/virtio.o
CC mips64-softmmu/hw/timer/mc146818rtc.o
CC mips-softmmu/gdbstub.o
CC mips64-softmmu/hw/vfio/common.o
CC mips64el-softmmu/hw/virtio/virtio-balloon.o
CC mipsel-softmmu/cputlb.o
CC mips64-softmmu/hw/vfio/pci.o
CC mips64el-softmmu/hw/virtio/vhost.o
CC mips-softmmu/balloon.o
CC mips-softmmu/ioport.o
CC mips64el-softmmu/hw/virtio/vhost-backend.o
CC mips-softmmu/numa.o
CC mips64-softmmu/hw/vfio/pci-quirks.o
CC mips64el-softmmu/hw/virtio/vhost-user.o
CC mipsel-softmmu/memory_mapping.o
CC mips-softmmu/qtest.o
CC mipsel-softmmu/dump.o
CC mips64el-softmmu/hw/virtio/vhost-vsock.o
CC mips64-softmmu/hw/vfio/platform.o
CC mips-softmmu/bootdevice.o
CC mips64-softmmu/hw/vfio/spapr.o
CC mips64el-softmmu/hw/virtio/virtio-crypto.o
CC mips-softmmu/memory.o
CC mipsel-softmmu/migration/ram.o
CC mips64-softmmu/hw/virtio/virtio.o
CC mips64el-softmmu/hw/virtio/virtio-crypto-pci.o
CC mipsel-softmmu/migration/savevm.o
CC mips64el-softmmu/hw/mips/mips_r4k.o
CC mips-softmmu/cputlb.o
CC mips64-softmmu/hw/virtio/virtio-balloon.o
CC mips64el-softmmu/hw/mips/mips_malta.o
CC mips64-softmmu/hw/virtio/vhost.o
CC mipsel-softmmu/xen-common-stub.o
CC mips64el-softmmu/hw/mips/mips_mipssim.o
CC mipsel-softmmu/xen-hvm-stub.o
CC mips64-softmmu/hw/virtio/vhost-backend.o
CC mips64el-softmmu/hw/mips/addr.o
CC mipsel-softmmu/hw/9pfs/virtio-9p-device.o
CC mips64-softmmu/hw/virtio/vhost-user.o
CC mips-softmmu/memory_mapping.o
CC mips64el-softmmu/hw/mips/cputimer.o
CC mips64el-softmmu/hw/mips/mips_int.o
CC mips-softmmu/dump.o
CC mipsel-softmmu/hw/block/virtio-blk.o
CC mips64-softmmu/hw/virtio/vhost-vsock.o
CC mips64el-softmmu/hw/mips/mips_jazz.o
CC mipsel-softmmu/hw/block/dataplane/virtio-blk.o
CC mips64-softmmu/hw/virtio/virtio-crypto.o
CC mips-softmmu/migration/ram.o
CC mips64el-softmmu/hw/mips/mips_fulong2e.o
CC mipsel-softmmu/hw/char/virtio-serial-bus.o
CC mips64el-softmmu/hw/mips/gt64xxx_pci.o
CC mips64-softmmu/hw/virtio/virtio-crypto-pci.o
CC mips64el-softmmu/hw/mips/cps.o
CC mips64-softmmu/hw/mips/mips_r4k.o
CC mips-softmmu/migration/savevm.o
CC mipsel-softmmu/hw/core/nmi.o
CC mips64el-softmmu/hw/mips/boston.o
CC mipsel-softmmu/hw/core/generic-loader.o
CC mips64-softmmu/hw/mips/mips_malta.o
CC mips64el-softmmu/target/mips/translate.o
CC mipsel-softmmu/hw/core/null-machine.o
CC mips64-softmmu/hw/mips/mips_mipssim.o
CC mips-softmmu/xen-common-stub.o
CC mips64-softmmu/hw/mips/addr.o
CC mipsel-softmmu/hw/cpu/core.o
CC mips-softmmu/xen-hvm-stub.o
CC mipsel-softmmu/hw/display/vga.o
CC mips64-softmmu/hw/mips/cputimer.o
CC mips-softmmu/hw/9pfs/virtio-9p-device.o
CC mips64-softmmu/hw/mips/mips_int.o
CC mips-softmmu/hw/block/virtio-blk.o
CC mipsel-softmmu/hw/display/virtio-gpu.o
CC mips64-softmmu/hw/mips/mips_jazz.o
CC mips-softmmu/hw/block/dataplane/virtio-blk.o
CC mipsel-softmmu/hw/display/virtio-gpu-3d.o
CC mips64-softmmu/hw/mips/gt64xxx_pci.o
CC mips64-softmmu/hw/mips/cps.o
CC mips-softmmu/hw/char/virtio-serial-bus.o
CC mips64-softmmu/target/mips/translate.o
CC mipsel-softmmu/hw/display/virtio-gpu-pci.o
CC mips-softmmu/hw/core/nmi.o
CC mips-softmmu/hw/core/generic-loader.o
CC mipsel-softmmu/hw/intc/mips_gic.o
CC mips-softmmu/hw/core/null-machine.o
CC mipsel-softmmu/hw/misc/ivshmem.o
CC mips-softmmu/hw/cpu/core.o
CC mipsel-softmmu/hw/misc/mips_cmgcr.o
CC mips-softmmu/hw/display/vga.o
CC mipsel-softmmu/hw/misc/mips_cpc.o
CC mipsel-softmmu/hw/misc/mips_itu.o
CC mips-softmmu/hw/display/virtio-gpu.o
CC mipsel-softmmu/hw/misc/edu.o
CC mips64el-softmmu/target/mips/dsp_helper.o
CC mipsel-softmmu/hw/net/virtio-net.o
CC mips-softmmu/hw/display/virtio-gpu-3d.o
CC mipsel-softmmu/hw/net/vhost_net.o
CC mips-softmmu/hw/display/virtio-gpu-pci.o
CC mipsel-softmmu/hw/scsi/virtio-scsi.o
CC mips64el-softmmu/target/mips/op_helper.o
CC mipsel-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC mips-softmmu/hw/intc/mips_gic.o
CC mipsel-softmmu/hw/scsi/vhost-scsi.o
CC mips-softmmu/hw/misc/ivshmem.o
CC mipsel-softmmu/hw/timer/mips_gictimer.o
CC mipsel-softmmu/hw/timer/mc146818rtc.o
CC mips-softmmu/hw/misc/mips_cmgcr.o
CC mipsel-softmmu/hw/vfio/common.o
CC mips-softmmu/hw/misc/mips_cpc.o
CC mips64-softmmu/target/mips/dsp_helper.o
CC mips-softmmu/hw/misc/mips_itu.o
CC mipsel-softmmu/hw/vfio/pci.o
CC mips64el-softmmu/target/mips/lmi_helper.o
CC mips-softmmu/hw/misc/edu.o
CC mips64el-softmmu/target/mips/helper.o
CC mips-softmmu/hw/net/virtio-net.o
CC mipsel-softmmu/hw/vfio/pci-quirks.o
CC mips64el-softmmu/target/mips/cpu.o
CC mips64-softmmu/target/mips/op_helper.o
CC mips64el-softmmu/target/mips/gdbstub.o
CC mips-softmmu/hw/net/vhost_net.o
CC mipsel-softmmu/hw/vfio/platform.o
CC mips64el-softmmu/target/mips/msa_helper.o
CC mips-softmmu/hw/scsi/virtio-scsi.o
CC mipsel-softmmu/hw/vfio/spapr.o
CC mips-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC mipsel-softmmu/hw/virtio/virtio.o
CC mips-softmmu/hw/scsi/vhost-scsi.o
CC mips-softmmu/hw/timer/mips_gictimer.o
CC mips-softmmu/hw/timer/mc146818rtc.o
CC mipsel-softmmu/hw/virtio/virtio-balloon.o
CC mips64-softmmu/target/mips/lmi_helper.o
CC mips-softmmu/hw/vfio/common.o
CC mipsel-softmmu/hw/virtio/vhost.o
CC mips64-softmmu/target/mips/helper.o
CC mips-softmmu/hw/vfio/pci.o
CC mipsel-softmmu/hw/virtio/vhost-backend.o
CC mips64-softmmu/target/mips/cpu.o
CC mips64-softmmu/target/mips/gdbstub.o
CC mipsel-softmmu/hw/virtio/vhost-user.o
CC mips64-softmmu/target/mips/msa_helper.o
CC mips64el-softmmu/target/mips/mips-semi.o
CC mipsel-softmmu/hw/virtio/vhost-vsock.o
CC mips-softmmu/hw/vfio/pci-quirks.o
CC mipsel-softmmu/hw/virtio/virtio-crypto.o
CC mips64el-softmmu/target/mips/machine.o
CC mips-softmmu/hw/vfio/platform.o
GEN trace/generated-helpers.c
CC mips64el-softmmu/trace/control-target.o
CC mipsel-softmmu/hw/virtio/virtio-crypto-pci.o
CC mips-softmmu/hw/vfio/spapr.o
CC mipsel-softmmu/hw/mips/mips_r4k.o
CC mips64el-softmmu/trace/generated-helpers.o
CC mips-softmmu/hw/virtio/virtio.o
CC mipsel-softmmu/hw/mips/mips_malta.o
LINK mips64el-softmmu/qemu-system-mips64el
CC mipsel-softmmu/hw/mips/mips_mipssim.o
CC mips-softmmu/hw/virtio/virtio-balloon.o
CC mipsel-softmmu/hw/mips/addr.o
CC mipsel-softmmu/hw/mips/cputimer.o
CC mips-softmmu/hw/virtio/vhost.o
CC mipsel-softmmu/hw/mips/mips_int.o
CC mipsel-softmmu/hw/mips/gt64xxx_pci.o
CC mips64-softmmu/target/mips/mips-semi.o
CC mipsel-softmmu/hw/mips/cps.o
CC mips-softmmu/hw/virtio/vhost-backend.o
CC mips-softmmu/hw/virtio/vhost-user.o
CC mips64-softmmu/target/mips/machine.o
CC mipsel-softmmu/target/mips/translate.o
CC mipsel-softmmu/target/mips/dsp_helper.o
GEN trace/generated-helpers.c
CC mips-softmmu/hw/virtio/vhost-vsock.o
CC mips64-softmmu/trace/control-target.o
CC mips64-softmmu/trace/generated-helpers.o
CC mips-softmmu/hw/virtio/virtio-crypto.o
LINK mips64-softmmu/qemu-system-mips64
CC mips-softmmu/hw/virtio/virtio-crypto-pci.o
CC mips-softmmu/hw/mips/mips_r4k.o
GEN moxie-softmmu/hmp-commands.h
GEN moxie-softmmu/hmp-commands-info.h
GEN moxie-softmmu/config-target.h
CC mips-softmmu/hw/mips/mips_malta.o
CC moxie-softmmu/exec.o
CC mipsel-softmmu/target/mips/op_helper.o
CC mips-softmmu/hw/mips/mips_mipssim.o
CC mips-softmmu/hw/mips/addr.o
CC mips-softmmu/hw/mips/cputimer.o
CC mips-softmmu/hw/mips/mips_int.o
CC mips-softmmu/hw/mips/gt64xxx_pci.o
CC mips-softmmu/hw/mips/cps.o
CC moxie-softmmu/translate-all.o
CC mipsel-softmmu/target/mips/lmi_helper.o
CC mips-softmmu/target/mips/translate.o
CC mipsel-softmmu/target/mips/helper.o
CC moxie-softmmu/cpu-exec.o
CC moxie-softmmu/translate-common.o
CC mips-softmmu/target/mips/dsp_helper.o
CC mipsel-softmmu/target/mips/cpu.o
CC moxie-softmmu/cpu-exec-common.o
CC mipsel-softmmu/target/mips/gdbstub.o
CC moxie-softmmu/tcg/tcg.o
CC mipsel-softmmu/target/mips/msa_helper.o
CC mips-softmmu/target/mips/op_helper.o
CC moxie-softmmu/tcg/tcg-op.o
CC moxie-softmmu/tcg/optimize.o
CC mips-softmmu/target/mips/lmi_helper.o
CC mipsel-softmmu/target/mips/mips-semi.o
CC moxie-softmmu/tcg/tcg-common.o
CC mipsel-softmmu/target/mips/machine.o
CC mips-softmmu/target/mips/helper.o
CC moxie-softmmu/fpu/softfloat.o
GEN trace/generated-helpers.c
CC mipsel-softmmu/trace/control-target.o
CC mips-softmmu/target/mips/cpu.o
GEN nios2-softmmu/hmp-commands.h
GEN nios2-softmmu/hmp-commands-info.h
GEN nios2-softmmu/config-target.h
CC nios2-softmmu/exec.o
CC mipsel-softmmu/trace/generated-helpers.o
CC mips-softmmu/target/mips/gdbstub.o
LINK mipsel-softmmu/qemu-system-mipsel
CC mips-softmmu/target/mips/msa_helper.o
CC moxie-softmmu/disas.o
GEN or1k-softmmu/hmp-commands.h
GEN or1k-softmmu/hmp-commands-info.h
GEN or1k-softmmu/config-target.h
CC or1k-softmmu/exec.o
CC nios2-softmmu/translate-all.o
CC moxie-softmmu/tcg-runtime.o
CC nios2-softmmu/cpu-exec.o
CC moxie-softmmu/hax-stub.o
CC nios2-softmmu/translate-common.o
CC moxie-softmmu/kvm-stub.o
CC moxie-softmmu/arch_init.o
CC nios2-softmmu/cpu-exec-common.o
CC or1k-softmmu/translate-all.o
CC mips-softmmu/target/mips/mips-semi.o
CC moxie-softmmu/cpus.o
CC nios2-softmmu/tcg/tcg.o
CC mips-softmmu/target/mips/machine.o
CC or1k-softmmu/cpu-exec.o
CC moxie-softmmu/monitor.o
GEN trace/generated-helpers.c
CC mips-softmmu/trace/control-target.o
CC or1k-softmmu/translate-common.o
CC mips-softmmu/trace/generated-helpers.o
CC or1k-softmmu/cpu-exec-common.o
CC nios2-softmmu/tcg/tcg-op.o
LINK mips-softmmu/qemu-system-mips
CC or1k-softmmu/tcg/tcg.o
CC moxie-softmmu/gdbstub.o
CC moxie-softmmu/balloon.o
CC moxie-softmmu/ioport.o
CC or1k-softmmu/tcg/tcg-op.o
CC moxie-softmmu/numa.o
CC nios2-softmmu/tcg/optimize.o
GEN ppc64-softmmu/hmp-commands.h
GEN ppc64-softmmu/hmp-commands-info.h
GEN ppc64-softmmu/config-target.h
CC moxie-softmmu/qtest.o
CC ppc64-softmmu/exec.o
CC nios2-softmmu/tcg/tcg-common.o
CC nios2-softmmu/fpu/softfloat.o
CC moxie-softmmu/bootdevice.o
CC or1k-softmmu/tcg/optimize.o
CC moxie-softmmu/memory.o
CC or1k-softmmu/tcg/tcg-common.o
CC moxie-softmmu/cputlb.o
CC or1k-softmmu/fpu/softfloat.o
CC ppc64-softmmu/translate-all.o
CC ppc64-softmmu/cpu-exec.o
CC nios2-softmmu/disas.o
CC moxie-softmmu/memory_mapping.o
CC ppc64-softmmu/translate-common.o
CC moxie-softmmu/dump.o
CC ppc64-softmmu/cpu-exec-common.o
CC nios2-softmmu/tcg-runtime.o
CC ppc64-softmmu/tcg/tcg.o
CC nios2-softmmu/hax-stub.o
CC moxie-softmmu/migration/ram.o
CC nios2-softmmu/kvm-stub.o
CC or1k-softmmu/disas.o
CC nios2-softmmu/arch_init.o
CC moxie-softmmu/migration/savevm.o
CC or1k-softmmu/tcg-runtime.o
CC nios2-softmmu/cpus.o
CC or1k-softmmu/hax-stub.o
CC moxie-softmmu/xen-common-stub.o
CC or1k-softmmu/kvm-stub.o
CC ppc64-softmmu/tcg/tcg-op.o
CC moxie-softmmu/xen-hvm-stub.o
CC nios2-softmmu/monitor.o
CC moxie-softmmu/hw/core/nmi.o
CC or1k-softmmu/arch_init.o
CC moxie-softmmu/hw/core/generic-loader.o
CC or1k-softmmu/cpus.o
CC moxie-softmmu/hw/core/null-machine.o
CC moxie-softmmu/hw/cpu/core.o
CC nios2-softmmu/gdbstub.o
CC or1k-softmmu/monitor.o
CC moxie-softmmu/hw/display/vga.o
CC nios2-softmmu/balloon.o
CC ppc64-softmmu/tcg/optimize.o
CC nios2-softmmu/ioport.o
CC moxie-softmmu/hw/net/vhost_net.o
CC nios2-softmmu/numa.o
CC or1k-softmmu/gdbstub.o
CC moxie-softmmu/hw/net/rocker/qmp-norocker.o
CC ppc64-softmmu/tcg/tcg-common.o
CC nios2-softmmu/qtest.o
CC or1k-softmmu/balloon.o
CC moxie-softmmu/hw/timer/mc146818rtc.o
CC ppc64-softmmu/fpu/softfloat.o
CC or1k-softmmu/ioport.o
CC nios2-softmmu/bootdevice.o
CC moxie-softmmu/hw/vfio/common.o
CC nios2-softmmu/memory.o
CC or1k-softmmu/numa.o
CC moxie-softmmu/hw/vfio/platform.o
CC or1k-softmmu/qtest.o
CC moxie-softmmu/hw/vfio/spapr.o
CC nios2-softmmu/cputlb.o
CC or1k-softmmu/bootdevice.o
CC moxie-softmmu/hw/moxie/moxiesim.o
CC or1k-softmmu/memory.o
CC ppc64-softmmu/disas.o
CC moxie-softmmu/target/moxie/translate.o
CC ppc64-softmmu/tcg-runtime.o
GEN ppc64-softmmu/gdbstub-xml.c
CC moxie-softmmu/target/moxie/helper.o
CC nios2-softmmu/memory_mapping.o
CC moxie-softmmu/target/moxie/machine.o
CC moxie-softmmu/target/moxie/cpu.o
CC nios2-softmmu/dump.o
CC or1k-softmmu/cputlb.o
CC moxie-softmmu/target/moxie/mmu.o
CC ppc64-softmmu/hax-stub.o
CC nios2-softmmu/migration/ram.o
GEN trace/generated-helpers.c
CC ppc64-softmmu/kvm-stub.o
CC moxie-softmmu/trace/control-target.o
CC ppc64-softmmu/libdecnumber/decContext.o
CC moxie-softmmu/trace/generated-helpers.o
CC nios2-softmmu/migration/savevm.o
CC or1k-softmmu/memory_mapping.o
CC ppc64-softmmu/libdecnumber/decNumber.o
LINK moxie-softmmu/qemu-system-moxie
CC or1k-softmmu/dump.o
CC nios2-softmmu/xen-common-stub.o
CC nios2-softmmu/xen-hvm-stub.o
CC or1k-softmmu/migration/ram.o
CC nios2-softmmu/hw/core/nmi.o
CC ppc64-softmmu/libdecnumber/dpd/decimal32.o
CC nios2-softmmu/hw/core/generic-loader.o
CC nios2-softmmu/hw/core/null-machine.o
CC ppc64-softmmu/libdecnumber/dpd/decimal64.o
CC or1k-softmmu/migration/savevm.o
CC nios2-softmmu/hw/cpu/core.o
CC or1k-softmmu/xen-common-stub.o
CC ppc64-softmmu/libdecnumber/dpd/decimal128.o
CC nios2-softmmu/hw/intc/nios2_iic.o
CC ppc64-softmmu/arch_init.o
CC nios2-softmmu/hw/net/vhost_net.o
CC nios2-softmmu/hw/net/rocker/qmp-norocker.o
CC nios2-softmmu/hw/timer/altera_timer.o
CC ppc64-softmmu/cpus.o
CC or1k-softmmu/xen-hvm-stub.o
CC nios2-softmmu/hw/vfio/common.o
CC or1k-softmmu/hw/core/nmi.o
GEN ppcemb-softmmu/hmp-commands.h
CC ppc64-softmmu/monitor.o
GEN ppcemb-softmmu/hmp-commands-info.h
GEN ppcemb-softmmu/config-target.h
CC or1k-softmmu/hw/core/generic-loader.o
CC ppcemb-softmmu/exec.o
CC nios2-softmmu/hw/vfio/platform.o
CC or1k-softmmu/hw/core/null-machine.o
CC or1k-softmmu/hw/cpu/core.o
CC nios2-softmmu/hw/vfio/spapr.o
CC or1k-softmmu/hw/net/vhost_net.o
CC nios2-softmmu/hw/nios2/boot.o
CC or1k-softmmu/hw/net/rocker/qmp-norocker.o
CC ppc64-softmmu/gdbstub.o
CC nios2-softmmu/hw/nios2/cpu_pic.o
CC or1k-softmmu/hw/vfio/common.o
CC nios2-softmmu/hw/nios2/10m50_devboard.o
CC ppc64-softmmu/balloon.o
CC nios2-softmmu/target/nios2/translate.o
CC ppcemb-softmmu/translate-all.o
CC or1k-softmmu/hw/vfio/platform.o
CC ppc64-softmmu/ioport.o
CC ppcemb-softmmu/cpu-exec.o
CC or1k-softmmu/hw/vfio/spapr.o
CC nios2-softmmu/target/nios2/op_helper.o
CC ppc64-softmmu/numa.o
CC ppcemb-softmmu/translate-common.o
CC or1k-softmmu/hw/openrisc/pic_cpu.o
CC nios2-softmmu/target/nios2/helper.o
CC ppcemb-softmmu/cpu-exec-common.o
CC ppc64-softmmu/qtest.o
CC or1k-softmmu/hw/openrisc/cputimer.o
CC ppcemb-softmmu/tcg/tcg.o
CC nios2-softmmu/target/nios2/cpu.o
CC or1k-softmmu/hw/openrisc/openrisc_sim.o
CC ppc64-softmmu/bootdevice.o
CC or1k-softmmu/target/openrisc/machine.o
CC nios2-softmmu/target/nios2/mmu.o
CC or1k-softmmu/target/openrisc/cpu.o
CC ppc64-softmmu/memory.o
CC nios2-softmmu/target/nios2/monitor.o
CC or1k-softmmu/target/openrisc/exception.o
CC or1k-softmmu/target/openrisc/interrupt.o
GEN trace/generated-helpers.c
CC nios2-softmmu/trace/control-target.o
CC ppcemb-softmmu/tcg/tcg-op.o
CC or1k-softmmu/target/openrisc/mmu.o
CC ppc64-softmmu/cputlb.o
CC nios2-softmmu/trace/generated-helpers.o
CC or1k-softmmu/target/openrisc/translate.o
LINK nios2-softmmu/qemu-system-nios2
CC or1k-softmmu/target/openrisc/exception_helper.o
CC ppc64-softmmu/memory_mapping.o
CC or1k-softmmu/target/openrisc/fpu_helper.o
CC or1k-softmmu/target/openrisc/interrupt_helper.o
CC ppc64-softmmu/dump.o
CC or1k-softmmu/target/openrisc/mmu_helper.o
CC ppc64-softmmu/migration/ram.o
CC or1k-softmmu/target/openrisc/sys_helper.o
CC ppcemb-softmmu/tcg/optimize.o
CC or1k-softmmu/target/openrisc/gdbstub.o
GEN trace/generated-helpers.c
GEN ppc-softmmu/hmp-commands.h
CC or1k-softmmu/trace/control-target.o
GEN ppc-softmmu/hmp-commands-info.h
GEN ppc-softmmu/config-target.h
CC ppc64-softmmu/migration/savevm.o
CC ppc-softmmu/exec.o
CC or1k-softmmu/trace/generated-helpers.o
CC ppcemb-softmmu/tcg/tcg-common.o
LINK or1k-softmmu/qemu-system-or1k
CC ppc64-softmmu/xen-common-stub.o
CC ppcemb-softmmu/fpu/softfloat.o
CC ppc64-softmmu/xen-hvm-stub.o
CC ppc64-softmmu/hw/9pfs/virtio-9p-device.o
CC ppc64-softmmu/hw/block/virtio-blk.o
CC ppc-softmmu/translate-all.o
CC ppcemb-softmmu/disas.o
CC ppc64-softmmu/hw/block/dataplane/virtio-blk.o
CC ppc-softmmu/cpu-exec.o
CC ppc64-softmmu/hw/char/spapr_vty.o
CC ppc-softmmu/translate-common.o
GEN s390x-softmmu/hmp-commands.h
CC ppc64-softmmu/hw/char/virtio-serial-bus.o
GEN s390x-softmmu/hmp-commands-info.h
CC s390x-softmmu/gen-features
CC ppcemb-softmmu/tcg-runtime.o
CC ppc-softmmu/cpu-exec-common.o
GEN s390x-softmmu/config-target.h
GEN s390x-softmmu/gen-features.h
CC s390x-softmmu/exec.o
CC ppc-softmmu/tcg/tcg.o
GEN ppcemb-softmmu/gdbstub-xml.c
CC ppc64-softmmu/hw/core/nmi.o
CC ppc64-softmmu/hw/core/generic-loader.o
CC ppcemb-softmmu/hax-stub.o
CC ppc64-softmmu/hw/core/null-machine.o
CC ppc-softmmu/tcg/tcg-op.o
CC ppcemb-softmmu/kvm-stub.o
CC ppc64-softmmu/hw/cpu/core.o
CC s390x-softmmu/translate-all.o
CC ppcemb-softmmu/libdecnumber/decContext.o
CC ppc64-softmmu/hw/display/vga.o
CC s390x-softmmu/cpu-exec.o
CC ppcemb-softmmu/libdecnumber/decNumber.o
CC s390x-softmmu/translate-common.o
CC s390x-softmmu/cpu-exec-common.o
CC s390x-softmmu/tcg/tcg.o
CC ppc64-softmmu/hw/display/virtio-gpu.o
CC ppc64-softmmu/hw/display/virtio-gpu-3d.o
CC ppcemb-softmmu/libdecnumber/dpd/decimal32.o
CC ppc-softmmu/tcg/optimize.o
CC ppcemb-softmmu/libdecnumber/dpd/decimal64.o
CC s390x-softmmu/tcg/tcg-op.o
CC ppcemb-softmmu/libdecnumber/dpd/decimal128.o
CC ppc64-softmmu/hw/display/virtio-gpu-pci.o
CC ppcemb-softmmu/arch_init.o
CC ppc64-softmmu/hw/display/virtio-vga.o
CC ppc-softmmu/tcg/tcg-common.o
CC ppcemb-softmmu/cpus.o
CC ppc64-softmmu/hw/intc/xics.o
CC ppc-softmmu/fpu/softfloat.o
CC ppc64-softmmu/hw/intc/xics_spapr.o
CC ppcemb-softmmu/monitor.o
CC ppc64-softmmu/hw/misc/ivshmem.o
CC ppc64-softmmu/hw/misc/edu.o
CC s390x-softmmu/tcg/optimize.o
CC ppc64-softmmu/hw/net/spapr_llan.o
CC ppcemb-softmmu/gdbstub.o
CC s390x-softmmu/tcg/tcg-common.o
CC ppc64-softmmu/hw/net/xilinx_ethlite.o
CC ppcemb-softmmu/balloon.o
CC s390x-softmmu/fpu/softfloat.o
CC ppc64-softmmu/hw/net/virtio-net.o
CC ppc-softmmu/disas.o
CC ppcemb-softmmu/ioport.o
CC ppc-softmmu/tcg-runtime.o
CC ppcemb-softmmu/numa.o
GEN ppc-softmmu/gdbstub-xml.c
CC ppcemb-softmmu/qtest.o
CC ppc64-softmmu/hw/net/vhost_net.o
CC ppcemb-softmmu/bootdevice.o
CC ppc64-softmmu/hw/net/fsl_etsec/etsec.o
CC ppc-softmmu/hax-stub.o
CC ppc64-softmmu/hw/net/fsl_etsec/registers.o
CC ppc-softmmu/kvm-stub.o
CC ppcemb-softmmu/memory.o
CC ppc-softmmu/libdecnumber/decContext.o
CC ppc64-softmmu/hw/net/fsl_etsec/rings.o
CC ppc-softmmu/libdecnumber/decNumber.o
CC ppc64-softmmu/hw/net/fsl_etsec/miim.o
CC s390x-softmmu/disas.o
CC ppc64-softmmu/hw/nvram/spapr_nvram.o
CC s390x-softmmu/tcg-runtime.o
CC ppcemb-softmmu/cputlb.o
CC ppc64-softmmu/hw/scsi/spapr_vscsi.o
GEN s390x-softmmu/gdbstub-xml.c
CC ppc64-softmmu/hw/scsi/virtio-scsi.o
CC ppc64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC ppc-softmmu/libdecnumber/dpd/decimal32.o
CC ppc64-softmmu/hw/scsi/vhost-scsi.o
CC s390x-softmmu/hax-stub.o
CC ppc-softmmu/libdecnumber/dpd/decimal64.o
CC ppc64-softmmu/hw/timer/mc146818rtc.o
CC s390x-softmmu/arch_init.o
CC ppcemb-softmmu/memory_mapping.o
CC ppc-softmmu/libdecnumber/dpd/decimal128.o
CC s390x-softmmu/cpus.o
CC ppc64-softmmu/hw/vfio/common.o
CC ppcemb-softmmu/dump.o
CC ppc-softmmu/arch_init.o
CC ppc64-softmmu/hw/vfio/pci.o
CC s390x-softmmu/monitor.o
CC ppc-softmmu/cpus.o
CC ppcemb-softmmu/migration/ram.o
CC ppc-softmmu/monitor.o
CC ppc64-softmmu/hw/vfio/pci-quirks.o
CC ppcemb-softmmu/migration/savevm.o
CC s390x-softmmu/gdbstub.o
CC ppc64-softmmu/hw/vfio/platform.o
CC ppc-softmmu/gdbstub.o
CC ppc64-softmmu/hw/vfio/spapr.o
CC s390x-softmmu/balloon.o
CC ppc64-softmmu/hw/virtio/virtio.o
CC ppcemb-softmmu/xen-common-stub.o
CC s390x-softmmu/ioport.o
CC ppc-softmmu/balloon.o
CC s390x-softmmu/numa.o
CC ppcemb-softmmu/xen-hvm-stub.o
CC ppc-softmmu/ioport.o
CC s390x-softmmu/qtest.o
CC ppcemb-softmmu/hw/9pfs/virtio-9p-device.o
CC ppc-softmmu/numa.o
CC ppc64-softmmu/hw/virtio/virtio-balloon.o
CC s390x-softmmu/bootdevice.o
CC ppcemb-softmmu/hw/block/virtio-blk.o
CC s390x-softmmu/kvm-all.o
CC ppc-softmmu/qtest.o
CC ppc64-softmmu/hw/virtio/vhost.o
CC ppcemb-softmmu/hw/block/dataplane/virtio-blk.o
CC ppc-softmmu/bootdevice.o
CC ppcemb-softmmu/hw/char/virtio-serial-bus.o
CC s390x-softmmu/memory.o
CC ppc-softmmu/memory.o
CC ppc64-softmmu/hw/virtio/vhost-backend.o
CC ppcemb-softmmu/hw/core/nmi.o
CC ppc64-softmmu/hw/virtio/vhost-user.o
CC ppcemb-softmmu/hw/core/generic-loader.o
CC s390x-softmmu/cputlb.o
CC ppc64-softmmu/hw/virtio/vhost-vsock.o
CC ppc-softmmu/cputlb.o
CC ppcemb-softmmu/hw/core/null-machine.o
CC ppc64-softmmu/hw/virtio/virtio-crypto.o
CC ppcemb-softmmu/hw/cpu/core.o
CC ppc64-softmmu/hw/virtio/virtio-crypto-pci.o
CC ppcemb-softmmu/hw/display/vga.o
CC ppc64-softmmu/hw/ppc/ppc.o
CC ppc64-softmmu/hw/ppc/ppc_booke.o
CC ppcemb-softmmu/hw/display/virtio-gpu.o
CC ppc64-softmmu/hw/ppc/fdt.o
CC s390x-softmmu/memory_mapping.o
CC ppc64-softmmu/hw/ppc/spapr.o
CC ppc-softmmu/memory_mapping.o
CC s390x-softmmu/dump.o
CC ppcemb-softmmu/hw/display/virtio-gpu-3d.o
CC ppc-softmmu/dump.o
CC ppc64-softmmu/hw/ppc/spapr_vio.o
CC s390x-softmmu/migration/ram.o
CC ppc-softmmu/migration/ram.o
CC ppcemb-softmmu/hw/display/virtio-gpu-pci.o
CC ppc64-softmmu/hw/ppc/spapr_events.o
CC ppcemb-softmmu/hw/misc/ivshmem.o
CC s390x-softmmu/migration/savevm.o
CC ppc64-softmmu/hw/ppc/spapr_hcall.o
CC ppc-softmmu/migration/savevm.o
CC ppcemb-softmmu/hw/misc/edu.o
CC ppc64-softmmu/hw/ppc/spapr_iommu.o
CC s390x-softmmu/xen-common-stub.o
CC ppcemb-softmmu/hw/net/xilinx_ethlite.o
CC ppc-softmmu/xen-common-stub.o
CC s390x-softmmu/xen-hvm-stub.o
CC ppc64-softmmu/hw/ppc/spapr_rtas.o
CC ppcemb-softmmu/hw/net/virtio-net.o
CC ppc-softmmu/xen-hvm-stub.o
CC s390x-softmmu/hw/9pfs/virtio-9p-device.o
CC ppc-softmmu/hw/9pfs/virtio-9p-device.o
CC ppc64-softmmu/hw/ppc/spapr_pci.o
CC s390x-softmmu/hw/block/virtio-blk.o
CC ppc-softmmu/hw/block/virtio-blk.o
CC ppcemb-softmmu/hw/net/vhost_net.o
CC ppcemb-softmmu/hw/scsi/virtio-scsi.o
CC s390x-softmmu/hw/block/dataplane/virtio-blk.o
CC ppc64-softmmu/hw/ppc/spapr_rtc.o
CC ppc-softmmu/hw/block/dataplane/virtio-blk.o
CC s390x-softmmu/hw/char/virtio-serial-bus.o
CC ppc64-softmmu/hw/ppc/spapr_drc.o
CC ppcemb-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC ppc-softmmu/hw/char/virtio-serial-bus.o
CC s390x-softmmu/hw/core/nmi.o
CC ppcemb-softmmu/hw/scsi/vhost-scsi.o
CC ppc64-softmmu/hw/ppc/spapr_rng.o
CC ppc-softmmu/hw/core/nmi.o
CC s390x-softmmu/hw/core/generic-loader.o
CC ppc-softmmu/hw/core/generic-loader.o
CC ppc64-softmmu/hw/ppc/spapr_cpu_core.o
CC s390x-softmmu/hw/core/null-machine.o
CC ppcemb-softmmu/hw/vfio/common.o
CC ppc-softmmu/hw/core/null-machine.o
CC s390x-softmmu/hw/cpu/core.o
CC ppc64-softmmu/hw/ppc/spapr_ovec.o
CC s390x-softmmu/hw/display/virtio-gpu.o
CC ppc-softmmu/hw/cpu/core.o
CC ppc64-softmmu/hw/ppc/pnv.o
CC ppc-softmmu/hw/display/vga.o
CC ppcemb-softmmu/hw/vfio/pci.o
CC ppc64-softmmu/hw/ppc/pnv_xscom.o
CC s390x-softmmu/hw/display/virtio-gpu-3d.o
CC ppc64-softmmu/hw/ppc/pnv_core.o
CC ppc-softmmu/hw/display/virtio-gpu.o
CC ppc64-softmmu/hw/ppc/pnv_lpc.o
CC ppcemb-softmmu/hw/vfio/pci-quirks.o
CC s390x-softmmu/hw/display/virtio-gpu-pci.o
CC ppc64-softmmu/hw/ppc/spapr_pci_vfio.o
CC s390x-softmmu/hw/intc/s390_flic.o
CC ppc64-softmmu/hw/ppc/spapr_rtas_ddw.o
CC s390x-softmmu/hw/intc/s390_flic_kvm.o
CC ppcemb-softmmu/hw/vfio/platform.o
CC ppc-softmmu/hw/display/virtio-gpu-3d.o
CC ppc64-softmmu/hw/ppc/ppc405_boards.o
CC s390x-softmmu/hw/net/virtio-net.o
CC ppcemb-softmmu/hw/vfio/spapr.o
CC ppc64-softmmu/hw/ppc/ppc4xx_devs.o
CC ppc-softmmu/hw/display/virtio-gpu-pci.o
CC ppcemb-softmmu/hw/virtio/virtio.o
CC ppc64-softmmu/hw/ppc/ppc405_uc.o
CC s390x-softmmu/hw/net/vhost_net.o
CC ppc-softmmu/hw/misc/ivshmem.o
CC s390x-softmmu/hw/net/rocker/qmp-norocker.o
CC ppc64-softmmu/hw/ppc/ppc440_bamboo.o
CC ppc-softmmu/hw/misc/edu.o
CC s390x-softmmu/hw/scsi/virtio-scsi.o
CC ppcemb-softmmu/hw/virtio/virtio-balloon.o
CC ppc-softmmu/hw/net/xilinx_ethlite.o
CC s390x-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC ppc64-softmmu/hw/ppc/ppc4xx_pci.o
CC s390x-softmmu/hw/scsi/vhost-scsi.o
CC ppcemb-softmmu/hw/virtio/vhost.o
CC ppc-softmmu/hw/net/virtio-net.o
CC ppc64-softmmu/hw/ppc/prep.o
CC s390x-softmmu/hw/vfio/common.o
CC ppc-softmmu/hw/net/vhost_net.o
CC ppc64-softmmu/hw/ppc/prep_systemio.o
CC ppcemb-softmmu/hw/virtio/vhost-backend.o
CC ppc-softmmu/hw/net/fsl_etsec/etsec.o
CC s390x-softmmu/hw/vfio/pci.o
CC ppcemb-softmmu/hw/virtio/vhost-user.o
CC ppc64-softmmu/hw/ppc/rs6000_mc.o
CC ppc-softmmu/hw/net/fsl_etsec/registers.o
CC ppcemb-softmmu/hw/virtio/vhost-vsock.o
CC ppc-softmmu/hw/net/fsl_etsec/rings.o
CC ppc64-softmmu/hw/ppc/mac_oldworld.o
CC ppcemb-softmmu/hw/virtio/virtio-crypto.o
CC ppc-softmmu/hw/net/fsl_etsec/miim.o
CC s390x-softmmu/hw/vfio/pci-quirks.o
CC ppcemb-softmmu/hw/virtio/virtio-crypto-pci.o
CC ppc64-softmmu/hw/ppc/mac_newworld.o
CC ppc-softmmu/hw/scsi/virtio-scsi.o
CC ppcemb-softmmu/hw/ppc/ppc.o
CC ppc64-softmmu/hw/ppc/e500.o
CC ppc-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC s390x-softmmu/hw/vfio/platform.o
CC ppc-softmmu/hw/scsi/vhost-scsi.o
CC ppcemb-softmmu/hw/ppc/ppc_booke.o
CC ppc64-softmmu/hw/ppc/mpc8544ds.o
CC s390x-softmmu/hw/vfio/spapr.o
CC s390x-softmmu/hw/virtio/virtio.o
CC ppc64-softmmu/hw/ppc/e500plat.o
CC ppcemb-softmmu/hw/ppc/fdt.o
CC ppc-softmmu/hw/timer/mc146818rtc.o
CC ppc64-softmmu/hw/ppc/mpc8544_guts.o
CC ppcemb-softmmu/hw/ppc/ppc405_boards.o
CC ppc64-softmmu/hw/ppc/ppce500_spin.o
CC ppc-softmmu/hw/vfio/common.o
CC ppcemb-softmmu/hw/ppc/ppc4xx_devs.o
CC s390x-softmmu/hw/virtio/virtio-balloon.o
CC ppc64-softmmu/hw/ppc/virtex_ml507.o
CC ppcemb-softmmu/hw/ppc/ppc405_uc.o
CC ppc-softmmu/hw/vfio/pci.o
CC ppc64-softmmu/target/ppc/cpu-models.o
CC s390x-softmmu/hw/virtio/vhost.o
CC ppcemb-softmmu/hw/ppc/ppc440_bamboo.o
CC ppcemb-softmmu/hw/ppc/ppc4xx_pci.o
CC s390x-softmmu/hw/virtio/vhost-backend.o
CC ppcemb-softmmu/hw/ppc/virtex_ml507.o
CC s390x-softmmu/hw/virtio/vhost-user.o
CC ppcemb-softmmu/target/ppc/cpu-models.o
CC ppc-softmmu/hw/vfio/pci-quirks.o
CC s390x-softmmu/hw/virtio/vhost-vsock.o
CC s390x-softmmu/hw/virtio/virtio-crypto.o
CC ppc64-softmmu/target/ppc/translate.o
CC ppc-softmmu/hw/vfio/platform.o
CC s390x-softmmu/hw/virtio/virtio-crypto-pci.o
CC ppc-softmmu/hw/vfio/spapr.o
CC s390x-softmmu/hw/s390x/s390-virtio.o
CC ppc-softmmu/hw/virtio/virtio.o
CC ppcemb-softmmu/target/ppc/translate.o
CC s390x-softmmu/hw/s390x/s390-virtio-hcall.o
CC s390x-softmmu/hw/s390x/sclp.o
CC s390x-softmmu/hw/s390x/event-facility.o
CC s390x-softmmu/hw/s390x/sclpquiesce.o
CC ppc-softmmu/hw/virtio/virtio-balloon.o
CC s390x-softmmu/hw/s390x/sclpcpu.o
CC ppc-softmmu/hw/virtio/vhost.o
CC s390x-softmmu/hw/s390x/ipl.o
CC s390x-softmmu/hw/s390x/css.o
CC ppc-softmmu/hw/virtio/vhost-backend.o
CC ppc-softmmu/hw/virtio/vhost-user.o
CC s390x-softmmu/hw/s390x/s390-virtio-ccw.o
CC ppc-softmmu/hw/virtio/vhost-vsock.o
CC s390x-softmmu/hw/s390x/virtio-ccw.o
CC ppc-softmmu/hw/virtio/virtio-crypto.o
CC ppc-softmmu/hw/virtio/virtio-crypto-pci.o
CC s390x-softmmu/hw/s390x/css-bridge.o
CC ppc-softmmu/hw/ppc/ppc.o
CC s390x-softmmu/hw/s390x/ccw-device.o
CC s390x-softmmu/hw/s390x/s390-pci-bus.o
CC ppc-softmmu/hw/ppc/ppc_booke.o
CC ppc-softmmu/hw/ppc/fdt.o
CC s390x-softmmu/hw/s390x/s390-pci-inst.o
CC ppc-softmmu/hw/ppc/ppc405_boards.o
CC s390x-softmmu/hw/s390x/s390-skeys.o
CC ppc-softmmu/hw/ppc/ppc4xx_devs.o
CC s390x-softmmu/hw/s390x/s390-skeys-kvm.o
CC ppc-softmmu/hw/ppc/ppc405_uc.o
CC s390x-softmmu/target/s390x/translate.o
CC ppc-softmmu/hw/ppc/ppc440_bamboo.o
CC ppc-softmmu/hw/ppc/ppc4xx_pci.o
CC ppc-softmmu/hw/ppc/prep.o
CC ppc-softmmu/hw/ppc/prep_systemio.o
CC ppc-softmmu/hw/ppc/rs6000_mc.o
CC s390x-softmmu/target/s390x/helper.o
CC ppc-softmmu/hw/ppc/mac_oldworld.o
CC s390x-softmmu/target/s390x/cpu.o
CC ppc-softmmu/hw/ppc/mac_newworld.o
CC ppcemb-softmmu/target/ppc/machine.o
CC s390x-softmmu/target/s390x/interrupt.o
CC ppc-softmmu/hw/ppc/e500.o
CC s390x-softmmu/target/s390x/int_helper.o
CC ppcemb-softmmu/target/ppc/mmu_helper.o
CC ppc64-softmmu/target/ppc/machine.o
CC s390x-softmmu/target/s390x/fpu_helper.o
CC ppc-softmmu/hw/ppc/mpc8544ds.o
CC ppc-softmmu/hw/ppc/e500plat.o
CC ppc64-softmmu/target/ppc/mmu_helper.o
CC ppc-softmmu/hw/ppc/mpc8544_guts.o
CC ppcemb-softmmu/target/ppc/mmu-hash32.o
CC s390x-softmmu/target/s390x/cc_helper.o
CC ppc-softmmu/hw/ppc/ppce500_spin.o
CC ppcemb-softmmu/target/ppc/monitor.o
CC s390x-softmmu/target/s390x/mem_helper.o
CC ppc-softmmu/hw/ppc/virtex_ml507.o
CC ppcemb-softmmu/target/ppc/kvm-stub.o
CC ppc64-softmmu/target/ppc/mmu-hash32.o
CC ppcemb-softmmu/target/ppc/dfp_helper.o
CC ppc-softmmu/target/ppc/cpu-models.o
CC ppc64-softmmu/target/ppc/monitor.o
CC s390x-softmmu/target/s390x/misc_helper.o
CC ppcemb-softmmu/target/ppc/excp_helper.o
CC ppc64-softmmu/target/ppc/mmu-hash64.o
CC s390x-softmmu/target/s390x/gdbstub.o
CC ppc64-softmmu/target/ppc/arch_dump.o
CC ppcemb-softmmu/target/ppc/fpu_helper.o
CC s390x-softmmu/target/s390x/cpu_models.o
CC ppc64-softmmu/target/ppc/compat.o
CC ppc-softmmu/target/ppc/translate.o
CC s390x-softmmu/target/s390x/cpu_features.o
CC ppc64-softmmu/target/ppc/kvm-stub.o
CC s390x-softmmu/target/s390x/machine.o
CC ppc64-softmmu/target/ppc/dfp_helper.o
CC s390x-softmmu/target/s390x/ioinst.o
CC s390x-softmmu/target/s390x/arch_dump.o
CC ppc64-softmmu/target/ppc/excp_helper.o
CC s390x-softmmu/target/s390x/mmu_helper.o
CC s390x-softmmu/target/s390x/kvm.o
CC ppc64-softmmu/target/ppc/fpu_helper.o
GEN trace/generated-helpers.c
CC s390x-softmmu/trace/control-target.o
CC s390x-softmmu/gdbstub-xml.o
CC ppcemb-softmmu/target/ppc/int_helper.o
CC s390x-softmmu/trace/generated-helpers.o
LINK s390x-softmmu/qemu-system-s390x
CC ppcemb-softmmu/target/ppc/timebase_helper.o
CC ppc-softmmu/target/ppc/machine.o
CC ppcemb-softmmu/target/ppc/misc_helper.o
CC ppc-softmmu/target/ppc/mmu_helper.o
CC ppcemb-softmmu/target/ppc/mem_helper.o
CC ppc64-softmmu/target/ppc/int_helper.o
CC ppc64-softmmu/target/ppc/timebase_helper.o
CC ppcemb-softmmu/target/ppc/gdbstub.o
GEN trace/generated-helpers.c
CC ppcemb-softmmu/trace/control-target.o
CC ppcemb-softmmu/gdbstub-xml.o
GEN sh4eb-softmmu/hmp-commands.h
GEN sh4eb-softmmu/hmp-commands-info.h
GEN sh4eb-softmmu/config-target.h
CC sh4eb-softmmu/exec.o
CC ppc64-softmmu/target/ppc/misc_helper.o
CC ppcemb-softmmu/trace/generated-helpers.o
CC ppc64-softmmu/target/ppc/mem_helper.o
LINK ppcemb-softmmu/qemu-system-ppcemb
CC ppc64-softmmu/target/ppc/gdbstub.o
GEN trace/generated-helpers.c
CC ppc64-softmmu/trace/control-target.o
CC sh4eb-softmmu/translate-all.o
CC ppc64-softmmu/gdbstub-xml.o
CC sh4eb-softmmu/cpu-exec.o
CC sh4eb-softmmu/translate-common.o
CC ppc64-softmmu/trace/generated-helpers.o
CC ppc-softmmu/target/ppc/mmu-hash32.o
CC ppc-softmmu/target/ppc/monitor.o
CC sh4eb-softmmu/cpu-exec-common.o
CC sh4eb-softmmu/tcg/tcg.o
LINK ppc64-softmmu/qemu-system-ppc64
CC ppc-softmmu/target/ppc/kvm-stub.o
CC ppc-softmmu/target/ppc/dfp_helper.o
CC sh4eb-softmmu/tcg/tcg-op.o
CC ppc-softmmu/target/ppc/excp_helper.o
CC ppc-softmmu/target/ppc/fpu_helper.o
CC sh4eb-softmmu/tcg/optimize.o
GEN sh4-softmmu/hmp-commands.h
GEN sh4-softmmu/hmp-commands-info.h
GEN sh4-softmmu/config-target.h
CC sh4-softmmu/exec.o
CC sh4eb-softmmu/tcg/tcg-common.o
GEN sparc64-softmmu/hmp-commands.h
CC sh4eb-softmmu/fpu/softfloat.o
GEN sparc64-softmmu/hmp-commands-info.h
GEN sparc64-softmmu/config-target.h
CC sparc64-softmmu/exec.o
CC sh4-softmmu/translate-all.o
CC sh4-softmmu/cpu-exec.o
CC sh4-softmmu/translate-common.o
CC ppc-softmmu/target/ppc/int_helper.o
CC sparc64-softmmu/translate-all.o
CC sh4-softmmu/cpu-exec-common.o
CC sh4eb-softmmu/disas.o
CC sh4-softmmu/tcg/tcg.o
CC sh4eb-softmmu/tcg-runtime.o
CC sparc64-softmmu/cpu-exec.o
CC sh4eb-softmmu/hax-stub.o
CC sparc64-softmmu/translate-common.o
CC sh4eb-softmmu/kvm-stub.o
CC ppc-softmmu/target/ppc/timebase_helper.o
CC sparc64-softmmu/cpu-exec-common.o
CC ppc-softmmu/target/ppc/misc_helper.o
CC sh4eb-softmmu/arch_init.o
CC sparc64-softmmu/tcg/tcg.o
CC sh4-softmmu/tcg/tcg-op.o
CC ppc-softmmu/target/ppc/mem_helper.o
CC sh4eb-softmmu/cpus.o
CC sh4eb-softmmu/monitor.o
CC ppc-softmmu/target/ppc/gdbstub.o
GEN trace/generated-helpers.c
CC sparc64-softmmu/tcg/tcg-op.o
CC ppc-softmmu/trace/control-target.o
CC ppc-softmmu/gdbstub-xml.o
CC sh4-softmmu/tcg/optimize.o
CC sh4eb-softmmu/gdbstub.o
CC ppc-softmmu/trace/generated-helpers.o
LINK ppc-softmmu/qemu-system-ppc
CC sh4-softmmu/tcg/tcg-common.o
CC sh4eb-softmmu/balloon.o
CC sh4-softmmu/fpu/softfloat.o
CC sh4eb-softmmu/ioport.o
CC sh4eb-softmmu/numa.o
CC sparc64-softmmu/tcg/optimize.o
CC sh4eb-softmmu/qtest.o
GEN sparc-softmmu/hmp-commands.h
GEN sparc-softmmu/hmp-commands-info.h
GEN sparc-softmmu/config-target.h
CC sparc-softmmu/exec.o
CC sparc64-softmmu/tcg/tcg-common.o
CC sh4eb-softmmu/bootdevice.o
CC sparc64-softmmu/fpu/softfloat.o
CC sh4eb-softmmu/memory.o
CC sh4-softmmu/disas.o
CC sh4-softmmu/tcg-runtime.o
CC sh4-softmmu/hax-stub.o
CC sh4-softmmu/kvm-stub.o
CC sh4eb-softmmu/cputlb.o
CC sh4-softmmu/arch_init.o
CC sparc-softmmu/translate-all.o
CC sh4-softmmu/cpus.o
CC sparc-softmmu/cpu-exec.o
CC sparc-softmmu/translate-common.o
CC sh4-softmmu/monitor.o
CC sh4eb-softmmu/memory_mapping.o
CC sparc-softmmu/cpu-exec-common.o
CC sparc64-softmmu/disas.o
CC sh4eb-softmmu/dump.o
CC sparc-softmmu/tcg/tcg.o
CC sparc64-softmmu/tcg-runtime.o
CC sparc64-softmmu/hax-stub.o
CC sh4-softmmu/gdbstub.o
CC sh4eb-softmmu/migration/ram.o
CC sparc64-softmmu/kvm-stub.o
CC sh4-softmmu/balloon.o
CC sparc64-softmmu/arch_init.o
CC sh4-softmmu/ioport.o
CC sparc64-softmmu/cpus.o
CC sh4eb-softmmu/migration/savevm.o
CC sparc-softmmu/tcg/tcg-op.o
CC sh4-softmmu/numa.o
CC sh4-softmmu/qtest.o
CC sparc64-softmmu/monitor.o
CC sh4eb-softmmu/xen-common-stub.o
CC sh4-softmmu/bootdevice.o
CC sh4eb-softmmu/xen-hvm-stub.o
CC sh4-softmmu/memory.o
CC sh4eb-softmmu/hw/9pfs/virtio-9p-device.o
CC sh4eb-softmmu/hw/block/tc58128.o
CC sparc64-softmmu/gdbstub.o
CC sh4-softmmu/cputlb.o
CC sh4eb-softmmu/hw/block/virtio-blk.o
CC sparc-softmmu/tcg/optimize.o
CC sparc64-softmmu/balloon.o
CC sh4eb-softmmu/hw/block/dataplane/virtio-blk.o
CC sparc64-softmmu/ioport.o
CC sparc64-softmmu/numa.o
CC sparc-softmmu/tcg/tcg-common.o
CC sh4eb-softmmu/hw/char/sh_serial.o
CC sparc-softmmu/fpu/softfloat.o
CC sh4eb-softmmu/hw/char/virtio-serial-bus.o
CC sparc64-softmmu/qtest.o
CC sh4-softmmu/memory_mapping.o
CC sh4eb-softmmu/hw/core/nmi.o
CC sparc64-softmmu/bootdevice.o
CC sh4-softmmu/dump.o
CC sh4eb-softmmu/hw/core/generic-loader.o
CC sparc64-softmmu/memory.o
CC sh4eb-softmmu/hw/core/null-machine.o
CC sh4-softmmu/migration/ram.o
CC sh4eb-softmmu/hw/cpu/core.o
CC sh4eb-softmmu/hw/display/sm501.o
CC sparc64-softmmu/cputlb.o
CC sh4-softmmu/migration/savevm.o
CC sparc-softmmu/disas.o
CC sh4eb-softmmu/hw/display/vga.o
CC sparc-softmmu/tcg-runtime.o
CC sh4-softmmu/xen-common-stub.o
CC sparc-softmmu/hax-stub.o
CC sh4eb-softmmu/hw/display/virtio-gpu.o
CC sparc-softmmu/kvm-stub.o
CC sh4-softmmu/xen-hvm-stub.o
CC sparc64-softmmu/memory_mapping.o
CC sparc-softmmu/arch_init.o
CC sh4-softmmu/hw/9pfs/virtio-9p-device.o
CC sparc64-softmmu/dump.o
CC sparc-softmmu/cpus.o
CC sh4-softmmu/hw/block/tc58128.o
CC sh4eb-softmmu/hw/display/virtio-gpu-3d.o
CC sh4-softmmu/hw/block/virtio-blk.o
CC sparc-softmmu/monitor.o
CC sparc64-softmmu/migration/ram.o
CC sh4eb-softmmu/hw/display/virtio-gpu-pci.o
CC sh4-softmmu/hw/block/dataplane/virtio-blk.o
CC sparc64-softmmu/migration/savevm.o
CC sh4eb-softmmu/hw/intc/sh_intc.o
CC sh4-softmmu/hw/char/sh_serial.o
CC sh4-softmmu/hw/char/virtio-serial-bus.o
CC sparc-softmmu/gdbstub.o
CC sh4eb-softmmu/hw/misc/ivshmem.o
CC sparc64-softmmu/xen-common-stub.o
CC sh4-softmmu/hw/core/nmi.o
CC sh4eb-softmmu/hw/misc/edu.o
CC sparc-softmmu/balloon.o
CC sparc64-softmmu/xen-hvm-stub.o
CC sh4-softmmu/hw/core/generic-loader.o
CC sh4eb-softmmu/hw/net/virtio-net.o
CC sparc64-softmmu/hw/9pfs/virtio-9p-device.o
CC sparc-softmmu/ioport.o
CC sh4-softmmu/hw/core/null-machine.o
CC sparc-softmmu/numa.o
CC sparc64-softmmu/hw/block/virtio-blk.o
CC sh4-softmmu/hw/cpu/core.o
CC sh4-softmmu/hw/display/sm501.o
CC sparc-softmmu/qtest.o
CC sh4eb-softmmu/hw/net/vhost_net.o
CC sparc64-softmmu/hw/block/dataplane/virtio-blk.o
CC sh4eb-softmmu/hw/scsi/virtio-scsi.o
CC sparc64-softmmu/hw/char/virtio-serial-bus.o
CC sparc-softmmu/bootdevice.o
CC sh4-softmmu/hw/display/vga.o
CC sparc-softmmu/memory.o
CC sh4eb-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC sparc64-softmmu/hw/core/nmi.o
CC sh4eb-softmmu/hw/scsi/vhost-scsi.o
CC sparc64-softmmu/hw/core/generic-loader.o
CC sh4-softmmu/hw/display/virtio-gpu.o
CC sh4eb-softmmu/hw/timer/sh_timer.o
CC sparc-softmmu/cputlb.o
CC sparc64-softmmu/hw/core/null-machine.o
CC sh4eb-softmmu/hw/timer/mc146818rtc.o
CC sparc64-softmmu/hw/cpu/core.o
CC sh4-softmmu/hw/display/virtio-gpu-3d.o
CC sparc64-softmmu/hw/display/vga.o
CC sh4eb-softmmu/hw/vfio/common.o
CC sparc-softmmu/memory_mapping.o
CC sh4-softmmu/hw/display/virtio-gpu-pci.o
CC sparc-softmmu/dump.o
CC sh4-softmmu/hw/intc/sh_intc.o
CC sh4eb-softmmu/hw/vfio/pci.o
CC sparc64-softmmu/hw/display/virtio-gpu.o
CC sh4-softmmu/hw/misc/ivshmem.o
CC sparc-softmmu/migration/ram.o
CC sh4-softmmu/hw/misc/edu.o
CC sparc64-softmmu/hw/display/virtio-gpu-3d.o
CC sh4-softmmu/hw/net/virtio-net.o
CC sh4eb-softmmu/hw/vfio/pci-quirks.o
CC sparc-softmmu/migration/savevm.o
CC sparc64-softmmu/hw/display/virtio-gpu-pci.o
CC sh4eb-softmmu/hw/vfio/platform.o
CC sh4-softmmu/hw/net/vhost_net.o
CC sh4eb-softmmu/hw/vfio/spapr.o
CC sparc64-softmmu/hw/misc/ivshmem.o
CC sh4-softmmu/hw/scsi/virtio-scsi.o
CC sh4eb-softmmu/hw/virtio/virtio.o
CC sparc-softmmu/xen-common-stub.o
CC sparc64-softmmu/hw/misc/edu.o
CC sparc-softmmu/xen-hvm-stub.o
CC sh4-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC sparc-softmmu/hw/core/nmi.o
CC sh4-softmmu/hw/scsi/vhost-scsi.o
CC sparc64-softmmu/hw/net/virtio-net.o
CC sparc-softmmu/hw/core/generic-loader.o
CC sh4eb-softmmu/hw/virtio/virtio-balloon.o
CC sh4-softmmu/hw/timer/sh_timer.o
CC sparc-softmmu/hw/core/null-machine.o
CC sh4-softmmu/hw/timer/mc146818rtc.o
CC sparc-softmmu/hw/cpu/core.o
CC sh4eb-softmmu/hw/virtio/vhost.o
CC sh4-softmmu/hw/vfio/common.o
CC sparc-softmmu/hw/display/tcx.o
CC sparc64-softmmu/hw/net/vhost_net.o
CC sparc64-softmmu/hw/scsi/virtio-scsi.o
CC sh4eb-softmmu/hw/virtio/vhost-backend.o
CC sh4-softmmu/hw/vfio/pci.o
CC sh4eb-softmmu/hw/virtio/vhost-user.o
CC sparc64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC sparc-softmmu/hw/display/cg3.o
CC sparc64-softmmu/hw/scsi/vhost-scsi.o
CC sh4eb-softmmu/hw/virtio/vhost-vsock.o
CC sparc64-softmmu/hw/timer/mc146818rtc.o
CC sparc-softmmu/hw/intc/grlib_irqmp.o
CC sparc64-softmmu/hw/vfio/common.o
CC sh4eb-softmmu/hw/virtio/virtio-crypto.o
CC sparc-softmmu/hw/misc/eccmemctl.o
CC sh4-softmmu/hw/vfio/pci-quirks.o
CC sh4eb-softmmu/hw/virtio/virtio-crypto-pci.o
CC sparc64-softmmu/hw/vfio/pci.o
CC sparc-softmmu/hw/misc/slavio_misc.o
CC sh4-softmmu/hw/vfio/platform.o
CC sh4eb-softmmu/hw/sh4/shix.o
CC sh4-softmmu/hw/vfio/spapr.o
CC sparc-softmmu/hw/net/vhost_net.o
CC sh4-softmmu/hw/virtio/virtio.o
CC sparc64-softmmu/hw/vfio/pci-quirks.o
CC sh4eb-softmmu/hw/sh4/r2d.o
CC sparc-softmmu/hw/net/rocker/qmp-norocker.o
CC sparc-softmmu/hw/vfio/common.o
CC sh4eb-softmmu/hw/sh4/sh7750.o
CC sparc64-softmmu/hw/vfio/platform.o
CC sh4-softmmu/hw/virtio/virtio-balloon.o
CC sparc-softmmu/hw/vfio/platform.o
CC sh4eb-softmmu/hw/sh4/sh7750_regnames.o
CC sparc64-softmmu/hw/vfio/spapr.o
CC sh4-softmmu/hw/virtio/vhost.o
CC sparc-softmmu/hw/vfio/spapr.o
CC sh4eb-softmmu/hw/sh4/sh_pci.o
CC sparc64-softmmu/hw/virtio/virtio.o
CC sparc-softmmu/hw/sparc/sun4m.o
CC sh4eb-softmmu/target/sh4/translate.o
CC sh4-softmmu/hw/virtio/vhost-backend.o
CC sparc-softmmu/hw/sparc/leon3.o
CC sh4-softmmu/hw/virtio/vhost-user.o
CC sparc64-softmmu/hw/virtio/virtio-balloon.o
CC sh4-softmmu/hw/virtio/vhost-vsock.o
CC sparc-softmmu/target/sparc/machine.o
CC sparc64-softmmu/hw/virtio/vhost.o
CC sh4-softmmu/hw/virtio/virtio-crypto.o
CC sparc-softmmu/target/sparc/monitor.o
CC sh4-softmmu/hw/virtio/virtio-crypto-pci.o
CC sparc-softmmu/target/sparc/translate.o
CC sparc64-softmmu/hw/virtio/vhost-backend.o
CC sh4-softmmu/hw/sh4/shix.o
CC sh4-softmmu/hw/sh4/r2d.o
CC sparc64-softmmu/hw/virtio/vhost-user.o
CC sh4eb-softmmu/target/sh4/op_helper.o
CC sh4-softmmu/hw/sh4/sh7750.o
CC sh4-softmmu/hw/sh4/sh7750_regnames.o
CC sparc64-softmmu/hw/virtio/vhost-vsock.o
CC sh4eb-softmmu/target/sh4/helper.o
CC sh4-softmmu/hw/sh4/sh_pci.o
CC sparc-softmmu/target/sparc/helper.o
CC sparc64-softmmu/hw/virtio/virtio-crypto.o
CC sparc-softmmu/target/sparc/cpu.o
CC sh4-softmmu/target/sh4/translate.o
CC sh4eb-softmmu/target/sh4/cpu.o
CC sparc64-softmmu/hw/virtio/virtio-crypto-pci.o
CC sparc-softmmu/target/sparc/fop_helper.o
CC sh4eb-softmmu/target/sh4/monitor.o
CC sparc-softmmu/target/sparc/cc_helper.o
CC sh4eb-softmmu/target/sh4/gdbstub.o
CC sparc64-softmmu/hw/sparc64/sparc64.o
CC sparc-softmmu/target/sparc/win_helper.o
CC sparc64-softmmu/hw/sparc64/sun4u.o
GEN trace/generated-helpers.c
CC sh4eb-softmmu/trace/control-target.o
CC sparc-softmmu/target/sparc/mmu_helper.o
CC sparc-softmmu/target/sparc/ldst_helper.o
CC sh4eb-softmmu/trace/generated-helpers.o
CC sparc-softmmu/target/sparc/int32_helper.o
CC sparc64-softmmu/hw/sparc64/niagara.o
CC sparc-softmmu/target/sparc/gdbstub.o
LINK sh4eb-softmmu/qemu-system-sh4eb
CC sparc64-softmmu/target/sparc/machine.o
GEN trace/generated-helpers.c
CC sparc-softmmu/trace/control-target.o
CC sh4-softmmu/target/sh4/op_helper.o
CC sparc64-softmmu/target/sparc/monitor.o
CC sparc-softmmu/trace/generated-helpers.o
CC sh4-softmmu/target/sh4/helper.o
CC sparc64-softmmu/target/sparc/translate.o
LINK sparc-softmmu/qemu-system-sparc
CC sh4-softmmu/target/sh4/cpu.o
CC sh4-softmmu/target/sh4/monitor.o
CC sh4-softmmu/target/sh4/gdbstub.o
GEN trace/generated-helpers.c
CC sh4-softmmu/trace/control-target.o
GEN tricore-softmmu/hmp-commands.h
GEN tricore-softmmu/hmp-commands-info.h
GEN tricore-softmmu/config-target.h
CC tricore-softmmu/exec.o
CC sh4-softmmu/trace/generated-helpers.o
GEN unicore32-softmmu/hmp-commands.h
GEN unicore32-softmmu/hmp-commands-info.h
GEN unicore32-softmmu/config-target.h
CC unicore32-softmmu/exec.o
LINK sh4-softmmu/qemu-system-sh4
CC sparc64-softmmu/target/sparc/helper.o
CC sparc64-softmmu/target/sparc/cpu.o
CC sparc64-softmmu/target/sparc/fop_helper.o
CC sparc64-softmmu/target/sparc/cc_helper.o
CC tricore-softmmu/translate-all.o
CC sparc64-softmmu/target/sparc/win_helper.o
CC tricore-softmmu/cpu-exec.o
CC sparc64-softmmu/target/sparc/mmu_helper.o
CC unicore32-softmmu/translate-all.o
CC sparc64-softmmu/target/sparc/ldst_helper.o
CC tricore-softmmu/translate-common.o
GEN x86_64-softmmu/hmp-commands.h
CC sparc64-softmmu/target/sparc/int64_helper.o
GEN x86_64-softmmu/hmp-commands-info.h
CC unicore32-softmmu/cpu-exec.o
GEN x86_64-softmmu/config-target.h
CC tricore-softmmu/cpu-exec-common.o
CC sparc64-softmmu/target/sparc/vis_helper.o
CC x86_64-softmmu/exec.o
CC tricore-softmmu/tcg/tcg.o
CC unicore32-softmmu/translate-common.o
CC sparc64-softmmu/target/sparc/gdbstub.o
CC unicore32-softmmu/cpu-exec-common.o
GEN trace/generated-helpers.c
CC sparc64-softmmu/trace/control-target.o
CC unicore32-softmmu/tcg/tcg.o
CC sparc64-softmmu/trace/generated-helpers.o
LINK sparc64-softmmu/qemu-system-sparc64
CC x86_64-softmmu/translate-all.o
CC tricore-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/cpu-exec.o
CC unicore32-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/translate-common.o
CC x86_64-softmmu/cpu-exec-common.o
CC x86_64-softmmu/tcg/tcg.o
GEN xtensaeb-softmmu/hmp-commands.h
GEN xtensaeb-softmmu/hmp-commands-info.h
GEN xtensaeb-softmmu/config-target.h
CC xtensaeb-softmmu/exec.o
CC tricore-softmmu/tcg/optimize.o
CC unicore32-softmmu/tcg/optimize.o
CC tricore-softmmu/tcg/tcg-common.o
CC x86_64-softmmu/tcg/tcg-op.o
CC tricore-softmmu/fpu/softfloat.o
CC xtensaeb-softmmu/translate-all.o
CC unicore32-softmmu/tcg/tcg-common.o
CC unicore32-softmmu/fpu/softfloat.o
CC xtensaeb-softmmu/cpu-exec.o
CC xtensaeb-softmmu/translate-common.o
CC xtensaeb-softmmu/cpu-exec-common.o
CC x86_64-softmmu/tcg/optimize.o
CC xtensaeb-softmmu/tcg/tcg.o
CC tricore-softmmu/disas.o
CC tricore-softmmu/tcg-runtime.o
CC tricore-softmmu/hax-stub.o
CC x86_64-softmmu/tcg/tcg-common.o
CC xtensaeb-softmmu/tcg/tcg-op.o
CC tricore-softmmu/kvm-stub.o
CC unicore32-softmmu/disas.o
CC x86_64-softmmu/fpu/softfloat.o
CC tricore-softmmu/arch_init.o
CC unicore32-softmmu/tcg-runtime.o
CC tricore-softmmu/cpus.o
CC unicore32-softmmu/hax-stub.o
CC unicore32-softmmu/kvm-stub.o
CC tricore-softmmu/monitor.o
CC unicore32-softmmu/arch_init.o
CC unicore32-softmmu/cpus.o
CC tricore-softmmu/gdbstub.o
CC xtensaeb-softmmu/tcg/optimize.o
CC unicore32-softmmu/monitor.o
CC x86_64-softmmu/disas.o
CC tricore-softmmu/balloon.o
CC x86_64-softmmu/tcg-runtime.o
CC tricore-softmmu/ioport.o
CC xtensaeb-softmmu/tcg/tcg-common.o
CC tricore-softmmu/numa.o
CC x86_64-softmmu/hax-stub.o
CC xtensaeb-softmmu/fpu/softfloat.o
CC x86_64-softmmu/kvm-stub.o
CC tricore-softmmu/qtest.o
CC x86_64-softmmu/arch_init.o
CC unicore32-softmmu/gdbstub.o
CC tricore-softmmu/bootdevice.o
CC x86_64-softmmu/cpus.o
CC unicore32-softmmu/balloon.o
CC tricore-softmmu/memory.o
CC unicore32-softmmu/ioport.o
CC x86_64-softmmu/monitor.o
CC unicore32-softmmu/numa.o
CC tricore-softmmu/cputlb.o
CC unicore32-softmmu/qtest.o
CC xtensaeb-softmmu/disas.o
CC xtensaeb-softmmu/tcg-runtime.o
CC unicore32-softmmu/bootdevice.o
CC x86_64-softmmu/gdbstub.o
CC xtensaeb-softmmu/hax-stub.o
CC unicore32-softmmu/memory.o
CC xtensaeb-softmmu/kvm-stub.o
CC tricore-softmmu/memory_mapping.o
CC xtensaeb-softmmu/arch_init.o
CC x86_64-softmmu/balloon.o
CC tricore-softmmu/dump.o
CC xtensaeb-softmmu/cpus.o
CC x86_64-softmmu/ioport.o
CC unicore32-softmmu/cputlb.o
CC x86_64-softmmu/numa.o
CC tricore-softmmu/migration/ram.o
CC xtensaeb-softmmu/monitor.o
CC x86_64-softmmu/qtest.o
CC x86_64-softmmu/bootdevice.o
CC tricore-softmmu/migration/savevm.o
CC unicore32-softmmu/memory_mapping.o
CC xtensaeb-softmmu/gdbstub.o
CC x86_64-softmmu/memory.o
CC unicore32-softmmu/dump.o
CC xtensaeb-softmmu/balloon.o
CC tricore-softmmu/xen-common-stub.o
CC tricore-softmmu/xen-hvm-stub.o
CC xtensaeb-softmmu/ioport.o
CC unicore32-softmmu/migration/ram.o
CC tricore-softmmu/hw/core/nmi.o
CC tricore-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/cputlb.o
CC xtensaeb-softmmu/numa.o
CC tricore-softmmu/hw/core/null-machine.o
CC unicore32-softmmu/migration/savevm.o
CC tricore-softmmu/hw/cpu/core.o
CC xtensaeb-softmmu/qtest.o
CC tricore-softmmu/hw/net/vhost_net.o
CC xtensaeb-softmmu/bootdevice.o
CC tricore-softmmu/hw/net/rocker/qmp-norocker.o
CC tricore-softmmu/hw/vfio/common.o
CC x86_64-softmmu/memory_mapping.o
CC xtensaeb-softmmu/memory.o
CC unicore32-softmmu/xen-common-stub.o
CC x86_64-softmmu/dump.o
CC tricore-softmmu/hw/vfio/platform.o
CC unicore32-softmmu/xen-hvm-stub.o
CC unicore32-softmmu/hw/core/nmi.o
CC tricore-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/migration/ram.o
CC tricore-softmmu/hw/tricore/tricore_testboard.o
CC unicore32-softmmu/hw/core/generic-loader.o
CC xtensaeb-softmmu/cputlb.o
CC tricore-softmmu/target/tricore/translate.o
CC unicore32-softmmu/hw/core/null-machine.o
CC x86_64-softmmu/migration/savevm.o
CC unicore32-softmmu/hw/cpu/core.o
CC unicore32-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/xen-common-stub.o
CC unicore32-softmmu/hw/net/rocker/qmp-norocker.o
CC xtensaeb-softmmu/memory_mapping.o
CC x86_64-softmmu/xen-hvm-stub.o
CC unicore32-softmmu/hw/vfio/common.o
CC xtensaeb-softmmu/dump.o
CC x86_64-softmmu/hw/9pfs/virtio-9p-device.o
CC unicore32-softmmu/hw/vfio/platform.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC xtensaeb-softmmu/migration/ram.o
CC unicore32-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC unicore32-softmmu/hw/unicore32/puv3.o
CC xtensaeb-softmmu/migration/savevm.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC unicore32-softmmu/target/unicore32/translate.o
CC x86_64-softmmu/hw/core/nmi.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC tricore-softmmu/target/tricore/helper.o
CC xtensaeb-softmmu/xen-common-stub.o
CC tricore-softmmu/target/tricore/cpu.o
CC x86_64-softmmu/hw/core/null-machine.o
CC xtensaeb-softmmu/xen-hvm-stub.o
CC unicore32-softmmu/target/unicore32/op_helper.o
CC tricore-softmmu/target/tricore/op_helper.o
CC x86_64-softmmu/hw/cpu/core.o
CC xtensaeb-softmmu/hw/core/nmi.o
CC unicore32-softmmu/target/unicore32/helper.o
CC x86_64-softmmu/hw/display/vga.o
CC xtensaeb-softmmu/hw/core/generic-loader.o
CC unicore32-softmmu/target/unicore32/cpu.o
CC xtensaeb-softmmu/hw/core/null-machine.o
CC unicore32-softmmu/target/unicore32/ucf64_helper.o
CC xtensaeb-softmmu/hw/cpu/core.o
CC tricore-softmmu/target/tricore/fpu_helper.o
CC unicore32-softmmu/target/unicore32/softmmu.o
CC xtensaeb-softmmu/hw/net/vhost_net.o
GEN trace/generated-helpers.c
CC tricore-softmmu/trace/control-target.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
GEN trace/generated-helpers.c
CC unicore32-softmmu/trace/control-target.o
CC xtensaeb-softmmu/hw/net/rocker/qmp-norocker.o
CC tricore-softmmu/trace/generated-helpers.o
CC xtensaeb-softmmu/hw/vfio/common.o
LINK tricore-softmmu/qemu-system-tricore
CC unicore32-softmmu/trace/generated-helpers.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
LINK unicore32-softmmu/qemu-system-unicore32
CC xtensaeb-softmmu/hw/vfio/platform.o
CC xtensaeb-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC xtensaeb-softmmu/hw/xtensa/pic_cpu.o
CC xtensaeb-softmmu/hw/xtensa/sim.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC x86_64-softmmu/hw/intc/apic.o
CC xtensaeb-softmmu/hw/xtensa/xtfpga.o
GEN xtensa-softmmu/hmp-commands.h
GEN xtensa-softmmu/hmp-commands-info.h
GEN xtensa-softmmu/config-target.h
CC xtensaeb-softmmu/target/xtensa/xtensa-semi.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC xtensa-softmmu/exec.o
CC xtensaeb-softmmu/target/xtensa/core-dc232b.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC xtensaeb-softmmu/target/xtensa/core-dc233c.o
CC xtensa-softmmu/translate-all.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC xtensaeb-softmmu/target/xtensa/core-fsf.o
CC xtensa-softmmu/cpu-exec.o
CC x86_64-softmmu/hw/misc/vmport.o
CC xtensa-softmmu/translate-common.o
CC xtensaeb-softmmu/target/xtensa/monitor.o
CC x86_64-softmmu/hw/misc/ivshmem.o
CC xtensa-softmmu/cpu-exec-common.o
CC xtensaeb-softmmu/target/xtensa/translate.o
CC xtensa-softmmu/tcg/tcg.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC x86_64-softmmu/hw/misc/edu.o
GEN aarch64-linux-user/config-target.h
CC x86_64-softmmu/hw/net/virtio-net.o
CC aarch64-linux-user/exec.o
CC aarch64-linux-user/translate-all.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC xtensaeb-softmmu/target/xtensa/op_helper.o
CC aarch64-linux-user/cpu-exec.o
CC xtensa-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/hw/scsi/vhost-scsi.o
CC aarch64-linux-user/translate-common.o
CC xtensaeb-softmmu/target/xtensa/helper.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC aarch64-linux-user/cpu-exec-common.o
CC xtensaeb-softmmu/target/xtensa/cpu.o
CC aarch64-linux-user/tcg/tcg.o
CC xtensaeb-softmmu/target/xtensa/gdbstub.o
CC x86_64-softmmu/hw/vfio/common.o
GEN trace/generated-helpers.c
CC xtensaeb-softmmu/trace/control-target.o
CC xtensa-softmmu/tcg/optimize.o
CC xtensaeb-softmmu/trace/generated-helpers.o
CC x86_64-softmmu/hw/vfio/pci.o
LINK xtensaeb-softmmu/qemu-system-xtensaeb
CC xtensa-softmmu/tcg/tcg-common.o
CC aarch64-linux-user/tcg/tcg-op.o
CC xtensa-softmmu/fpu/softfloat.o
CC x86_64-softmmu/hw/vfio/pci-quirks.o
CC x86_64-softmmu/hw/vfio/platform.o
GEN alpha-linux-user/config-target.h
CC alpha-linux-user/exec.o
CC x86_64-softmmu/hw/vfio/spapr.o
CC alpha-linux-user/translate-all.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC alpha-linux-user/cpu-exec.o
CC aarch64-linux-user/tcg/optimize.o
CC alpha-linux-user/translate-common.o
CC xtensa-softmmu/disas.o
CC alpha-linux-user/cpu-exec-common.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC xtensa-softmmu/tcg-runtime.o
CC alpha-linux-user/tcg/tcg.o
CC xtensa-softmmu/hax-stub.o
CC x86_64-softmmu/hw/virtio/vhost.o
CC aarch64-linux-user/tcg/tcg-common.o
CC xtensa-softmmu/kvm-stub.o
CC aarch64-linux-user/fpu/softfloat.o
CC xtensa-softmmu/arch_init.o
CC xtensa-softmmu/cpus.o
CC x86_64-softmmu/hw/virtio/vhost-backend.o
CC xtensa-softmmu/monitor.o
CC alpha-linux-user/tcg/tcg-op.o
CC x86_64-softmmu/hw/virtio/vhost-user.o
CC x86_64-softmmu/hw/virtio/vhost-vsock.o
CC x86_64-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-linux-user/disas.o
CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o
CC xtensa-softmmu/gdbstub.o
CC aarch64-linux-user/tcg-runtime.o
CC alpha-linux-user/tcg/optimize.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC x86_64-softmmu/hw/i386/pc.o
CC xtensa-softmmu/balloon.o
GEN aarch64-linux-user/gdbstub-xml.c
CC xtensa-softmmu/ioport.o
CC alpha-linux-user/tcg/tcg-common.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC xtensa-softmmu/numa.o
CC aarch64-linux-user/hax-stub.o
CC alpha-linux-user/fpu/softfloat.o
CC aarch64-linux-user/kvm-stub.o
CC xtensa-softmmu/qtest.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC aarch64-linux-user/gdbstub.o
CC xtensa-softmmu/bootdevice.o
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC xtensa-softmmu/memory.o
CC aarch64-linux-user/thunk.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC aarch64-linux-user/user-exec.o
CC aarch64-linux-user/user-exec-stub.o
CC xtensa-softmmu/cputlb.o
CC alpha-linux-user/disas.o
CC aarch64-linux-user/linux-user/main.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC alpha-linux-user/tcg-runtime.o
CC aarch64-linux-user/linux-user/syscall.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC alpha-linux-user/hax-stub.o
CC xtensa-softmmu/memory_mapping.o
CC alpha-linux-user/kvm-stub.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC xtensa-softmmu/dump.o
CC alpha-linux-user/gdbstub.o
CC xtensa-softmmu/migration/ram.o
CC alpha-linux-user/thunk.o
CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o
CC alpha-linux-user/user-exec.o
CC x86_64-softmmu/target/i386/translate.o
CC xtensa-softmmu/migration/savevm.o
CC alpha-linux-user/user-exec-stub.o
CC alpha-linux-user/linux-user/main.o
CC aarch64-linux-user/linux-user/strace.o
CC xtensa-softmmu/xen-common-stub.o
CC alpha-linux-user/linux-user/syscall.o
CC xtensa-softmmu/xen-hvm-stub.o
CC aarch64-linux-user/linux-user/mmap.o
CC xtensa-softmmu/hw/core/nmi.o
CC xtensa-softmmu/hw/core/generic-loader.o
CC aarch64-linux-user/linux-user/signal.o
CC xtensa-softmmu/hw/core/null-machine.o
CC aarch64-linux-user/linux-user/elfload.o
CC xtensa-softmmu/hw/cpu/core.o
CC xtensa-softmmu/hw/net/vhost_net.o
CC aarch64-linux-user/linux-user/linuxload.o
CC xtensa-softmmu/hw/net/rocker/qmp-norocker.o
CC xtensa-softmmu/hw/vfio/common.o
CC aarch64-linux-user/linux-user/uaccess.o
CC alpha-linux-user/linux-user/strace.o
CC aarch64-linux-user/linux-user/uname.o
CCAS aarch64-linux-user/linux-user/safe-syscall.o
CC xtensa-softmmu/hw/vfio/platform.o
CC aarch64-linux-user/linux-user/flatload.o
CC alpha-linux-user/linux-user/mmap.o
CC aarch64-linux-user/target/arm/arm-semi.o
CC xtensa-softmmu/hw/vfio/spapr.o
CC alpha-linux-user/linux-user/signal.o
CC x86_64-softmmu/target/i386/helper.o
CC aarch64-linux-user/target/arm/kvm-stub.o
CC xtensa-softmmu/hw/xtensa/pic_cpu.o
CC aarch64-linux-user/target/arm/translate.o
CC alpha-linux-user/linux-user/elfload.o
CC x86_64-softmmu/target/i386/cpu.o
CC xtensa-softmmu/hw/xtensa/sim.o
CC xtensa-softmmu/hw/xtensa/xtfpga.o
CC alpha-linux-user/linux-user/linuxload.o
CC xtensa-softmmu/target/xtensa/xtensa-semi.o
CC alpha-linux-user/linux-user/uaccess.o
CC x86_64-softmmu/target/i386/bpt_helper.o
CC alpha-linux-user/linux-user/uname.o
CC xtensa-softmmu/target/xtensa/core-dc232b.o
CC x86_64-softmmu/target/i386/excp_helper.o
CC xtensa-softmmu/target/xtensa/core-dc233c.o
CCAS alpha-linux-user/linux-user/safe-syscall.o
CC xtensa-softmmu/target/xtensa/core-fsf.o
CC x86_64-softmmu/target/i386/fpu_helper.o
CC alpha-linux-user/target/alpha/translate.o
CC xtensa-softmmu/target/xtensa/monitor.o
CC xtensa-softmmu/target/xtensa/translate.o
CC alpha-linux-user/target/alpha/helper.o
CC alpha-linux-user/target/alpha/cpu.o
CC alpha-linux-user/target/alpha/int_helper.o
CC xtensa-softmmu/target/xtensa/op_helper.o
CC alpha-linux-user/target/alpha/fpu_helper.o
CC x86_64-softmmu/target/i386/cc_helper.o
CC alpha-linux-user/target/alpha/vax_helper.o
CC xtensa-softmmu/target/xtensa/helper.o
CC x86_64-softmmu/target/i386/int_helper.o
CC aarch64-linux-user/target/arm/op_helper.o
CC alpha-linux-user/target/alpha/sys_helper.o
CC xtensa-softmmu/target/xtensa/cpu.o
CC alpha-linux-user/target/alpha/mem_helper.o
CC xtensa-softmmu/target/xtensa/gdbstub.o
CC x86_64-softmmu/target/i386/svm_helper.o
CC alpha-linux-user/target/alpha/gdbstub.o
CC aarch64-linux-user/target/arm/helper.o
GEN trace/generated-helpers.c
CC xtensa-softmmu/trace/control-target.o
GEN trace/generated-helpers.c
CC alpha-linux-user/trace/control-target.o
CC x86_64-softmmu/target/i386/smm_helper.o
CC xtensa-softmmu/trace/generated-helpers.o
CC alpha-linux-user/trace/generated-helpers.o
CC x86_64-softmmu/target/i386/misc_helper.o
LINK xtensa-softmmu/qemu-system-xtensa
LINK alpha-linux-user/qemu-alpha
CC x86_64-softmmu/target/i386/mem_helper.o
CC x86_64-softmmu/target/i386/seg_helper.o
GEN armeb-linux-user/config-target.h
CC armeb-linux-user/exec.o
CC aarch64-linux-user/target/arm/cpu.o
CC aarch64-linux-user/target/arm/neon_helper.o
GEN arm-linux-user/config-target.h
CC armeb-linux-user/translate-all.o
CC arm-linux-user/exec.o
CC arm-linux-user/translate-all.o
CC armeb-linux-user/cpu-exec.o
CC aarch64-linux-user/target/arm/iwmmxt_helper.o
CC arm-linux-user/cpu-exec.o
CC armeb-linux-user/translate-common.o
CC x86_64-softmmu/target/i386/mpx_helper.o
CC arm-linux-user/translate-common.o
CC armeb-linux-user/cpu-exec-common.o
CC aarch64-linux-user/target/arm/gdbstub.o
CC arm-linux-user/cpu-exec-common.o
CC x86_64-softmmu/target/i386/gdbstub.o
CC armeb-linux-user/tcg/tcg.o
CC aarch64-linux-user/target/arm/cpu64.o
CC arm-linux-user/tcg/tcg.o
CC x86_64-softmmu/target/i386/machine.o
CC aarch64-linux-user/target/arm/translate-a64.o
CC x86_64-softmmu/target/i386/arch_memory_mapping.o
CC x86_64-softmmu/target/i386/arch_dump.o
CC x86_64-softmmu/target/i386/monitor.o
CC armeb-linux-user/tcg/tcg-op.o
CC x86_64-softmmu/target/i386/kvm-stub.o
CC arm-linux-user/tcg/tcg-op.o
GEN trace/generated-helpers.c
CC x86_64-softmmu/trace/control-target.o
CC x86_64-softmmu/trace/generated-helpers.o
LINK x86_64-softmmu/qemu-system-x86_64
CC aarch64-linux-user/target/arm/helper-a64.o
CC armeb-linux-user/tcg/optimize.o
CC arm-linux-user/tcg/optimize.o
CC aarch64-linux-user/target/arm/gdbstub64.o
CC aarch64-linux-user/target/arm/crypto_helper.o
GEN trace/generated-helpers.c
CC aarch64-linux-user/trace/control-target.o
CC arm-linux-user/tcg/tcg-common.o
CC arm-linux-user/fpu/softfloat.o
CC armeb-linux-user/tcg/tcg-common.o
CC aarch64-linux-user/gdbstub-xml.o
CC arm-linux-user/disas.o
CC armeb-linux-user/fpu/softfloat.o
CC aarch64-linux-user/trace/generated-helpers.o
CC arm-linux-user/tcg-runtime.o
LINK aarch64-linux-user/qemu-aarch64
GEN arm-linux-user/gdbstub-xml.c
GEN cris-linux-user/config-target.h
CC cris-linux-user/exec.o
CC arm-linux-user/hax-stub.o
CC cris-linux-user/translate-all.o
CC cris-linux-user/cpu-exec.o
CC arm-linux-user/kvm-stub.o
CC armeb-linux-user/disas.o
CC arm-linux-user/gdbstub.o
CC armeb-linux-user/tcg-runtime.o
CC cris-linux-user/translate-common.o
CC cris-linux-user/cpu-exec-common.o
GEN armeb-linux-user/gdbstub-xml.c
CC armeb-linux-user/hax-stub.o
CC arm-linux-user/thunk.o
CC cris-linux-user/tcg/tcg.o
CC armeb-linux-user/kvm-stub.o
CC arm-linux-user/user-exec.o
CC cris-linux-user/tcg/tcg-op.o
CC arm-linux-user/user-exec-stub.o
CC armeb-linux-user/gdbstub.o
CC arm-linux-user/linux-user/main.o
CC armeb-linux-user/thunk.o
CC arm-linux-user/linux-user/syscall.o
CC armeb-linux-user/user-exec.o
CC armeb-linux-user/user-exec-stub.o
CC armeb-linux-user/linux-user/main.o
CC cris-linux-user/tcg/optimize.o
GEN hppa-linux-user/config-target.h
CC hppa-linux-user/exec.o
CC armeb-linux-user/linux-user/syscall.o
CC cris-linux-user/tcg/tcg-common.o
CC hppa-linux-user/translate-all.o
CC cris-linux-user/fpu/softfloat.o
CC hppa-linux-user/cpu-exec.o
CC hppa-linux-user/translate-common.o
CC hppa-linux-user/cpu-exec-common.o
CC hppa-linux-user/tcg/tcg.o
CC arm-linux-user/linux-user/strace.o
CC cris-linux-user/disas.o
CC arm-linux-user/linux-user/mmap.o
CC cris-linux-user/tcg-runtime.o
CC hppa-linux-user/tcg/tcg-op.o
CC arm-linux-user/linux-user/signal.o
CC armeb-linux-user/linux-user/strace.o
CC cris-linux-user/hax-stub.o
CC arm-linux-user/linux-user/elfload.o
CC cris-linux-user/kvm-stub.o
CC armeb-linux-user/linux-user/mmap.o
CC cris-linux-user/gdbstub.o
CC arm-linux-user/linux-user/linuxload.o
CC armeb-linux-user/linux-user/signal.o
CC cris-linux-user/thunk.o
CC arm-linux-user/linux-user/uaccess.o
CC armeb-linux-user/linux-user/elfload.o
CC cris-linux-user/user-exec.o
CC cris-linux-user/user-exec-stub.o
CC arm-linux-user/linux-user/uname.o
CC hppa-linux-user/tcg/optimize.o
CC cris-linux-user/linux-user/main.o
CCAS arm-linux-user/linux-user/safe-syscall.o
CC arm-linux-user/linux-user/flatload.o
CC armeb-linux-user/linux-user/linuxload.o
CC cris-linux-user/linux-user/syscall.o
CC arm-linux-user/linux-user/arm/nwfpe/fpa11.o
CC armeb-linux-user/linux-user/uaccess.o
CC hppa-linux-user/tcg/tcg-common.o
CC arm-linux-user/linux-user/arm/nwfpe/fpa11_cpdo.o
CC armeb-linux-user/linux-user/uname.o
CC hppa-linux-user/fpu/softfloat.o
CC arm-linux-user/linux-user/arm/nwfpe/fpa11_cpdt.o
CCAS armeb-linux-user/linux-user/safe-syscall.o
CC armeb-linux-user/linux-user/flatload.o
CC arm-linux-user/linux-user/arm/nwfpe/fpa11_cprt.o
CC armeb-linux-user/linux-user/arm/nwfpe/fpa11.o
CC arm-linux-user/linux-user/arm/nwfpe/fpopcode.o
CC armeb-linux-user/linux-user/arm/nwfpe/fpa11_cpdo.o
CC armeb-linux-user/linux-user/arm/nwfpe/fpa11_cpdt.o
CC arm-linux-user/linux-user/arm/nwfpe/single_cpdo.o
CC hppa-linux-user/disas.o
CC arm-linux-user/linux-user/arm/nwfpe/double_cpdo.o
CC armeb-linux-user/linux-user/arm/nwfpe/fpa11_cprt.o
CC hppa-linux-user/tcg-runtime.o
CC arm-linux-user/linux-user/arm/nwfpe/extended_cpdo.o
CC armeb-linux-user/linux-user/arm/nwfpe/fpopcode.o
CC arm-linux-user/target/arm/arm-semi.o
CC armeb-linux-user/linux-user/arm/nwfpe/single_cpdo.o
CC hppa-linux-user/hax-stub.o
CC cris-linux-user/linux-user/strace.o
CC armeb-linux-user/linux-user/arm/nwfpe/double_cpdo.o
CC hppa-linux-user/kvm-stub.o
CC arm-linux-user/target/arm/kvm-stub.o
CC armeb-linux-user/linux-user/arm/nwfpe/extended_cpdo.o
CC hppa-linux-user/gdbstub.o
CC arm-linux-user/target/arm/translate.o
CC cris-linux-user/linux-user/mmap.o
CC armeb-linux-user/target/arm/arm-semi.o
CC hppa-linux-user/thunk.o
CC cris-linux-user/linux-user/signal.o
CC armeb-linux-user/target/arm/kvm-stub.o
CC hppa-linux-user/user-exec.o
CC cris-linux-user/linux-user/elfload.o
CC armeb-linux-user/target/arm/translate.o
CC hppa-linux-user/user-exec-stub.o
CC hppa-linux-user/linux-user/main.o
CC cris-linux-user/linux-user/linuxload.o
CC hppa-linux-user/linux-user/syscall.o
CC cris-linux-user/linux-user/uaccess.o
CC cris-linux-user/linux-user/uname.o
CCAS cris-linux-user/linux-user/safe-syscall.o
CC cris-linux-user/target/cris/translate.o
CC arm-linux-user/target/arm/op_helper.o
CC cris-linux-user/target/cris/op_helper.o
CC hppa-linux-user/linux-user/strace.o
CC arm-linux-user/target/arm/helper.o
CC cris-linux-user/target/cris/helper.o
CC cris-linux-user/target/cris/cpu.o
CC hppa-linux-user/linux-user/mmap.o
CC cris-linux-user/target/cris/gdbstub.o
CC armeb-linux-user/target/arm/op_helper.o
GEN trace/generated-helpers.c
CC cris-linux-user/trace/control-target.o
CC hppa-linux-user/linux-user/signal.o
CC arm-linux-user/target/arm/cpu.o
CC hppa-linux-user/linux-user/elfload.o
CC cris-linux-user/trace/generated-helpers.o
CC armeb-linux-user/target/arm/helper.o
CC arm-linux-user/target/arm/neon_helper.o
LINK cris-linux-user/qemu-cris
CC hppa-linux-user/linux-user/linuxload.o
CC hppa-linux-user/linux-user/uaccess.o
CC armeb-linux-user/target/arm/cpu.o
CC hppa-linux-user/linux-user/uname.o
CCAS hppa-linux-user/linux-user/safe-syscall.o
CC armeb-linux-user/target/arm/neon_helper.o
CC arm-linux-user/target/arm/iwmmxt_helper.o
CC hppa-linux-user/target/hppa/translate.o
CC hppa-linux-user/target/hppa/helper.o
CC arm-linux-user/target/arm/gdbstub.o
GEN i386-linux-user/config-target.h
CC armeb-linux-user/target/arm/iwmmxt_helper.o
CC i386-linux-user/exec.o
CC arm-linux-user/target/arm/crypto_helper.o
CC hppa-linux-user/target/hppa/cpu.o
CC hppa-linux-user/target/hppa/op_helper.o
GEN trace/generated-helpers.c
CC arm-linux-user/trace/control-target.o
CC i386-linux-user/translate-all.o
CC hppa-linux-user/target/hppa/gdbstub.o
CC armeb-linux-user/target/arm/gdbstub.o
CC arm-linux-user/gdbstub-xml.o
CC armeb-linux-user/target/arm/crypto_helper.o
GEN trace/generated-helpers.c
CC arm-linux-user/trace/generated-helpers.o
CC hppa-linux-user/trace/control-target.o
CC i386-linux-user/cpu-exec.o
LINK arm-linux-user/qemu-arm
GEN trace/generated-helpers.c
CC armeb-linux-user/trace/control-target.o
CC hppa-linux-user/trace/generated-helpers.o
CC i386-linux-user/translate-common.o
CC armeb-linux-user/gdbstub-xml.o
LINK hppa-linux-user/qemu-hppa
CC i386-linux-user/cpu-exec-common.o
GEN m68k-linux-user/config-target.h
CC armeb-linux-user/trace/generated-helpers.o
CC i386-linux-user/tcg/tcg.o
CC m68k-linux-user/exec.o
LINK armeb-linux-user/qemu-armeb
GEN microblazeel-linux-user/config-target.h
CC m68k-linux-user/translate-all.o
CC microblazeel-linux-user/exec.o
CC microblazeel-linux-user/translate-all.o
CC microblazeel-linux-user/cpu-exec.o
CC m68k-linux-user/cpu-exec.o
CC microblazeel-linux-user/translate-common.o
CC microblazeel-linux-user/cpu-exec-common.o
CC microblazeel-linux-user/tcg/tcg.o
CC m68k-linux-user/translate-common.o
CC i386-linux-user/tcg/tcg-op.o
CC microblazeel-linux-user/tcg/tcg-op.o
CC m68k-linux-user/cpu-exec-common.o
CC m68k-linux-user/tcg/tcg.o
CC i386-linux-user/tcg/optimize.o
CC i386-linux-user/tcg/tcg-common.o
CC microblazeel-linux-user/tcg/optimize.o
CC i386-linux-user/fpu/softfloat.o
CC m68k-linux-user/tcg/tcg-op.o
CC i386-linux-user/disas.o
GEN microblaze-linux-user/config-target.h
CC microblazeel-linux-user/tcg/tcg-common.o
CC microblazeel-linux-user/fpu/softfloat.o
CC microblaze-linux-user/exec.o
CC microblaze-linux-user/translate-all.o
CC m68k-linux-user/tcg/optimize.o
CC microblaze-linux-user/cpu-exec.o
CC microblaze-linux-user/translate-common.o
CC m68k-linux-user/tcg/tcg-common.o
CC i386-linux-user/tcg-runtime.o
CC microblaze-linux-user/cpu-exec-common.o
CC m68k-linux-user/fpu/softfloat.o
CC microblaze-linux-user/tcg/tcg.o
CC i386-linux-user/hax-stub.o
CC microblazeel-linux-user/disas.o
CC i386-linux-user/kvm-stub.o
CC microblazeel-linux-user/tcg-runtime.o
CC i386-linux-user/gdbstub.o
CC microblazeel-linux-user/hax-stub.o
CC microblazeel-linux-user/kvm-stub.o
CC i386-linux-user/thunk.o
CC i386-linux-user/user-exec.o
CC microblazeel-linux-user/gdbstub.o
CC i386-linux-user/user-exec-stub.o
CC microblaze-linux-user/tcg/tcg-op.o
CC microblazeel-linux-user/thunk.o
CC i386-linux-user/linux-user/main.o
CC microblazeel-linux-user/user-exec.o
CC i386-linux-user/linux-user/syscall.o
CC microblazeel-linux-user/user-exec-stub.o
CC m68k-linux-user/disas.o
CC microblazeel-linux-user/linux-user/main.o
CC m68k-linux-user/tcg-runtime.o
CC microblazeel-linux-user/linux-user/syscall.o
GEN m68k-linux-user/gdbstub-xml.c
CC m68k-linux-user/hax-stub.o
CC microblaze-linux-user/tcg/optimize.o
CC m68k-linux-user/kvm-stub.o
CC m68k-linux-user/gdbstub.o
CC m68k-linux-user/thunk.o
CC microblaze-linux-user/tcg/tcg-common.o
CC microblaze-linux-user/fpu/softfloat.o
CC m68k-linux-user/user-exec.o
CC m68k-linux-user/user-exec-stub.o
CC m68k-linux-user/linux-user/main.o
CC m68k-linux-user/linux-user/syscall.o
CC microblazeel-linux-user/linux-user/strace.o
CC i386-linux-user/linux-user/strace.o
CC microblaze-linux-user/disas.o
CC microblaze-linux-user/tcg-runtime.o
CC microblazeel-linux-user/linux-user/mmap.o
CC i386-linux-user/linux-user/mmap.o
CC microblazeel-linux-user/linux-user/signal.o
CC microblaze-linux-user/hax-stub.o
CC i386-linux-user/linux-user/signal.o
CC microblaze-linux-user/kvm-stub.o
CC microblaze-linux-user/gdbstub.o
CC microblazeel-linux-user/linux-user/elfload.o
CC i386-linux-user/linux-user/elfload.o
CC microblaze-linux-user/thunk.o
CC microblazeel-linux-user/linux-user/linuxload.o
CC microblaze-linux-user/user-exec.o
CC i386-linux-user/linux-user/linuxload.o
CC microblazeel-linux-user/linux-user/uaccess.o
CC microblaze-linux-user/user-exec-stub.o
CC i386-linux-user/linux-user/uaccess.o
CC m68k-linux-user/linux-user/strace.o
CC microblazeel-linux-user/linux-user/uname.o
CC i386-linux-user/linux-user/uname.o
CC microblaze-linux-user/linux-user/main.o
CCAS microblazeel-linux-user/linux-user/safe-syscall.o
CC microblazeel-linux-user/linux-user/flatload.o
CCAS i386-linux-user/linux-user/safe-syscall.o
CC i386-linux-user/linux-user/vm86.o
CC microblaze-linux-user/linux-user/syscall.o
CC m68k-linux-user/linux-user/mmap.o
CC i386-linux-user/target/i386/translate.o
CC microblazeel-linux-user/target/microblaze/translate.o
CC m68k-linux-user/linux-user/signal.o
CC m68k-linux-user/linux-user/elfload.o
CC microblazeel-linux-user/target/microblaze/op_helper.o
CC microblazeel-linux-user/target/microblaze/helper.o
CC microblazeel-linux-user/target/microblaze/cpu.o
CC m68k-linux-user/linux-user/linuxload.o
CC microblazeel-linux-user/target/microblaze/gdbstub.o
CC m68k-linux-user/linux-user/uaccess.o
GEN trace/generated-helpers.c
CC microblazeel-linux-user/trace/control-target.o
CC m68k-linux-user/linux-user/uname.o
CCAS m68k-linux-user/linux-user/safe-syscall.o
CC m68k-linux-user/linux-user/flatload.o
CC microblazeel-linux-user/trace/generated-helpers.o
CC m68k-linux-user/linux-user/m68k-sim.o
CC m68k-linux-user/target/m68k/m68k-semi.o
LINK microblazeel-linux-user/qemu-microblazeel
CC m68k-linux-user/target/m68k/translate.o
CC microblaze-linux-user/linux-user/strace.o
GEN mips64el-linux-user/config-target.h
CC mips64el-linux-user/exec.o
CC microblaze-linux-user/linux-user/mmap.o
CC mips64el-linux-user/translate-all.o
CC microblaze-linux-user/linux-user/signal.o
CC i386-linux-user/target/i386/helper.o
CC mips64el-linux-user/cpu-exec.o
CC m68k-linux-user/target/m68k/op_helper.o
CC i386-linux-user/target/i386/cpu.o
CC microblaze-linux-user/linux-user/elfload.o
CC mips64el-linux-user/translate-common.o
CC m68k-linux-user/target/m68k/helper.o
CC mips64el-linux-user/cpu-exec-common.o
CC m68k-linux-user/target/m68k/cpu.o
CC i386-linux-user/target/i386/bpt_helper.o
CC microblaze-linux-user/linux-user/linuxload.o
CC mips64el-linux-user/tcg/tcg.o
CC m68k-linux-user/target/m68k/gdbstub.o
CC i386-linux-user/target/i386/excp_helper.o
CC microblaze-linux-user/linux-user/uaccess.o
GEN trace/generated-helpers.c
CC m68k-linux-user/trace/control-target.o
CC i386-linux-user/target/i386/fpu_helper.o
CC microblaze-linux-user/linux-user/uname.o
CC m68k-linux-user/gdbstub-xml.o
CCAS microblaze-linux-user/linux-user/safe-syscall.o
CC microblaze-linux-user/linux-user/flatload.o
CC m68k-linux-user/trace/generated-helpers.o
LINK m68k-linux-user/qemu-m68k
CC microblaze-linux-user/target/microblaze/translate.o
CC i386-linux-user/target/i386/cc_helper.o
CC mips64el-linux-user/tcg/tcg-op.o
CC mips64el-linux-user/tcg/optimize.o
CC i386-linux-user/target/i386/int_helper.o
CC microblaze-linux-user/target/microblaze/op_helper.o
CC i386-linux-user/target/i386/svm_helper.o
CC microblaze-linux-user/target/microblaze/helper.o
CC i386-linux-user/target/i386/smm_helper.o
CC i386-linux-user/target/i386/misc_helper.o
CC microblaze-linux-user/target/microblaze/cpu.o
CC microblaze-linux-user/target/microblaze/gdbstub.o
CC i386-linux-user/target/i386/mem_helper.o
GEN trace/generated-helpers.c
CC microblaze-linux-user/trace/control-target.o
CC i386-linux-user/target/i386/seg_helper.o
GEN mips64-linux-user/config-target.h
CC mips64el-linux-user/tcg/tcg-common.o
CC mips64-linux-user/exec.o
CC microblaze-linux-user/trace/generated-helpers.o
LINK microblaze-linux-user/qemu-microblaze
CC mips64el-linux-user/fpu/softfloat.o
CC mips64-linux-user/translate-all.o
CC mips64-linux-user/cpu-exec.o
GEN mipsel-linux-user/config-target.h
CC mipsel-linux-user/exec.o
CC mips64-linux-user/translate-common.o
CC mipsel-linux-user/translate-all.o
CC mips64-linux-user/cpu-exec-common.o
CC i386-linux-user/target/i386/mpx_helper.o
CC mipsel-linux-user/cpu-exec.o
CC mips64-linux-user/tcg/tcg.o
CC mipsel-linux-user/translate-common.o
CC mipsel-linux-user/cpu-exec-common.o
CC i386-linux-user/target/i386/gdbstub.o
CC mipsel-linux-user/tcg/tcg.o
CC i386-linux-user/target/i386/kvm-stub.o
GEN trace/generated-helpers.c
CC i386-linux-user/trace/control-target.o
CC mips64el-linux-user/disas.o
CC i386-linux-user/trace/generated-helpers.o
CC mips64el-linux-user/tcg-runtime.o
LINK i386-linux-user/qemu-i386
CC mips64-linux-user/tcg/tcg-op.o
CC mipsel-linux-user/tcg/tcg-op.o
CC mipsel-linux-user/tcg/optimize.o
CC mips64el-linux-user/hax-stub.o
CC mips64el-linux-user/kvm-stub.o
CC mips64el-linux-user/gdbstub.o
CC mips64-linux-user/tcg/optimize.o
CC mips64el-linux-user/thunk.o
CC mipsel-linux-user/tcg/tcg-common.o
CC mips64-linux-user/tcg/tcg-common.o
CC mips64el-linux-user/user-exec.o
CC mipsel-linux-user/fpu/softfloat.o
CC mips64el-linux-user/user-exec-stub.o
CC mipsel-linux-user/disas.o
CC mips64el-linux-user/linux-user/main.o
CC mips64-linux-user/fpu/softfloat.o
CC mips64-linux-user/disas.o
CC mips64el-linux-user/linux-user/syscall.o
CC mipsel-linux-user/tcg-runtime.o
CC mips64-linux-user/tcg-runtime.o
CC mipsel-linux-user/hax-stub.o
CC mips64el-linux-user/linux-user/strace.o
CC mipsel-linux-user/kvm-stub.o
CC mipsel-linux-user/gdbstub.o
GEN mips-linux-user/config-target.h
CC mips64-linux-user/hax-stub.o
CC mips-linux-user/exec.o
CC mipsel-linux-user/thunk.o
CC mips64-linux-user/kvm-stub.o
CC mips-linux-user/translate-all.o
CC mipsel-linux-user/user-exec.o
CC mips64el-linux-user/linux-user/mmap.o
CC mips64-linux-user/gdbstub.o
CC mipsel-linux-user/user-exec-stub.o
CC mips-linux-user/cpu-exec.o
CC mips64-linux-user/thunk.o
CC mips64el-linux-user/linux-user/signal.o
CC mipsel-linux-user/linux-user/main.o
CC mips-linux-user/translate-common.o
CC mips64-linux-user/user-exec.o
CC mips-linux-user/cpu-exec-common.o
CC mips64-linux-user/user-exec-stub.o
CC mipsel-linux-user/linux-user/syscall.o
CC mips64el-linux-user/linux-user/elfload.o
CC mips-linux-user/tcg/tcg.o
CC mips64-linux-user/linux-user/main.o
CC mips64-linux-user/linux-user/syscall.o
CC mips64el-linux-user/linux-user/linuxload.o
CC mips64el-linux-user/linux-user/uaccess.o
CC mips64el-linux-user/linux-user/uname.o
CC mips-linux-user/tcg/tcg-op.o
CCAS mips64el-linux-user/linux-user/safe-syscall.o
CC mips64el-linux-user/target/mips/translate.o
CC mips64-linux-user/linux-user/strace.o
CC mipsel-linux-user/linux-user/strace.o
CC mips64-linux-user/linux-user/mmap.o
CC mips-linux-user/tcg/optimize.o
CC mips64-linux-user/linux-user/signal.o
CC mipsel-linux-user/linux-user/mmap.o
CC mips64-linux-user/linux-user/elfload.o
CC mips-linux-user/tcg/tcg-common.o
CC mipsel-linux-user/linux-user/signal.o
CC mips-linux-user/fpu/softfloat.o
CC mips64-linux-user/linux-user/linuxload.o
CC mipsel-linux-user/linux-user/elfload.o
CC mips64-linux-user/linux-user/uaccess.o
CC mips64-linux-user/linux-user/uname.o
CC mipsel-linux-user/linux-user/linuxload.o
CCAS mips64-linux-user/linux-user/safe-syscall.o
CC mips64-linux-user/target/mips/translate.o
CC mips64el-linux-user/target/mips/dsp_helper.o
CC mipsel-linux-user/linux-user/uaccess.o
CC mipsel-linux-user/linux-user/uname.o
CC mips-linux-user/disas.o
CCAS mipsel-linux-user/linux-user/safe-syscall.o
CC mipsel-linux-user/target/mips/translate.o
CC mips-linux-user/tcg-runtime.o
CC mips64el-linux-user/target/mips/op_helper.o
CC mips-linux-user/hax-stub.o
CC mips-linux-user/kvm-stub.o
CC mips-linux-user/gdbstub.o
CC mips-linux-user/thunk.o
CC mips-linux-user/user-exec.o
CC mips64el-linux-user/target/mips/lmi_helper.o
CC mips-linux-user/user-exec-stub.o
CC mips64el-linux-user/target/mips/helper.o
CC mips-linux-user/linux-user/main.o
CC mips64el-linux-user/target/mips/cpu.o
CC mips-linux-user/linux-user/syscall.o
CC mips64-linux-user/target/mips/dsp_helper.o
CC mips64el-linux-user/target/mips/gdbstub.o
CC mips64el-linux-user/target/mips/msa_helper.o
CC mipsel-linux-user/target/mips/dsp_helper.o
CC mips64-linux-user/target/mips/op_helper.o
CC mipsel-linux-user/target/mips/op_helper.o
CC mips-linux-user/linux-user/strace.o
CC mips-linux-user/linux-user/mmap.o
CC mips64-linux-user/target/mips/lmi_helper.o
CC mips64el-linux-user/target/mips/mips-semi.o
CC mips-linux-user/linux-user/signal.o
GEN trace/generated-helpers.c
CC mips64el-linux-user/trace/control-target.o
CC mips64el-linux-user/trace/generated-helpers.o
CC mips64-linux-user/target/mips/helper.o
LINK mips64el-linux-user/qemu-mips64el
CC mips64-linux-user/target/mips/cpu.o
CC mips-linux-user/linux-user/elfload.o
CC mipsel-linux-user/target/mips/lmi_helper.o
CC mips-linux-user/linux-user/linuxload.o
CC mips64-linux-user/target/mips/gdbstub.o
CC mipsel-linux-user/target/mips/helper.o
CC mips64-linux-user/target/mips/msa_helper.o
CC mips-linux-user/linux-user/uaccess.o
CC mipsel-linux-user/target/mips/cpu.o
GEN mipsn32el-linux-user/config-target.h
CC mipsn32el-linux-user/exec.o
CC mips-linux-user/linux-user/uname.o
CC mipsel-linux-user/target/mips/gdbstub.o
CC mipsn32el-linux-user/translate-all.o
CCAS mips-linux-user/linux-user/safe-syscall.o
CC mips-linux-user/target/mips/translate.o
CC mipsel-linux-user/target/mips/msa_helper.o
CC mipsn32el-linux-user/cpu-exec.o
CC mipsn32el-linux-user/translate-common.o
CC mipsn32el-linux-user/cpu-exec-common.o
CC mipsn32el-linux-user/tcg/tcg.o
CC mips64-linux-user/target/mips/mips-semi.o
GEN trace/generated-helpers.c
CC mips64-linux-user/trace/control-target.o
CC mips64-linux-user/trace/generated-helpers.o
LINK mips64-linux-user/qemu-mips64
CC mipsel-linux-user/target/mips/mips-semi.o
CC mipsn32el-linux-user/tcg/tcg-op.o
GEN trace/generated-helpers.c
GEN mipsn32-linux-user/config-target.h
CC mipsel-linux-user/trace/control-target.o
CC mipsn32-linux-user/exec.o
CC mipsel-linux-user/trace/generated-helpers.o
CC mipsn32-linux-user/translate-all.o
LINK mipsel-linux-user/qemu-mipsel
CC mips-linux-user/target/mips/dsp_helper.o
CC mips-linux-user/target/mips/op_helper.o
CC mipsn32-linux-user/cpu-exec.o
CC mipsn32-linux-user/translate-common.o
GEN nios2-linux-user/config-target.h
CC mipsn32-linux-user/cpu-exec-common.o
CC nios2-linux-user/exec.o
CC mipsn32el-linux-user/tcg/optimize.o
CC mipsn32-linux-user/tcg/tcg.o
CC nios2-linux-user/translate-all.o
CC nios2-linux-user/cpu-exec.o
CC mips-linux-user/target/mips/lmi_helper.o
CC mipsn32el-linux-user/tcg/tcg-common.o
CC nios2-linux-user/translate-common.o
CC mips-linux-user/target/mips/helper.o
CC mipsn32el-linux-user/fpu/softfloat.o
CC nios2-linux-user/cpu-exec-common.o
CC mips-linux-user/target/mips/cpu.o
CC mipsn32-linux-user/tcg/tcg-op.o
CC nios2-linux-user/tcg/tcg.o
CC mips-linux-user/target/mips/gdbstub.o
CC mips-linux-user/target/mips/msa_helper.o
CC nios2-linux-user/tcg/tcg-op.o
CC mipsn32-linux-user/tcg/optimize.o
CC mipsn32el-linux-user/disas.o
CC mipsn32el-linux-user/tcg-runtime.o
CC mipsn32el-linux-user/hax-stub.o
CC mipsn32-linux-user/tcg/tcg-common.o
CC mipsn32-linux-user/fpu/softfloat.o
CC mipsn32el-linux-user/kvm-stub.o
CC mipsn32el-linux-user/gdbstub.o
CC nios2-linux-user/tcg/optimize.o
CC mips-linux-user/target/mips/mips-semi.o
GEN trace/generated-helpers.c
CC mipsn32el-linux-user/thunk.o
CC mips-linux-user/trace/control-target.o
CC nios2-linux-user/tcg/tcg-common.o
CC mips-linux-user/trace/generated-helpers.o
CC mipsn32el-linux-user/user-exec.o
CC nios2-linux-user/fpu/softfloat.o
CC mipsn32el-linux-user/user-exec-stub.o
LINK mips-linux-user/qemu-mips
CC mipsn32el-linux-user/linux-user/main.o
CC nios2-linux-user/disas.o
CC mipsn32-linux-user/disas.o
CC nios2-linux-user/tcg-runtime.o
CC mipsn32el-linux-user/linux-user/syscall.o
CC mipsn32-linux-user/tcg-runtime.o
CC mipsn32-linux-user/hax-stub.o
GEN or1k-linux-user/config-target.h
CC or1k-linux-user/exec.o
CC mipsn32-linux-user/kvm-stub.o
CC nios2-linux-user/hax-stub.o
CC nios2-linux-user/kvm-stub.o
CC or1k-linux-user/translate-all.o
CC mipsn32-linux-user/gdbstub.o
CC nios2-linux-user/gdbstub.o
CC or1k-linux-user/cpu-exec.o
CC or1k-linux-user/translate-common.o
CC nios2-linux-user/thunk.o
CC mipsn32-linux-user/thunk.o
CC or1k-linux-user/cpu-exec-common.o
CC or1k-linux-user/tcg/tcg.o
CC nios2-linux-user/user-exec.o
CC mipsn32-linux-user/user-exec.o
CC nios2-linux-user/user-exec-stub.o
CC mipsn32-linux-user/user-exec-stub.o
CC mipsn32el-linux-user/linux-user/strace.o
CC nios2-linux-user/linux-user/main.o
CC mipsn32-linux-user/linux-user/main.o
CC mipsn32el-linux-user/linux-user/mmap.o
CC nios2-linux-user/linux-user/syscall.o
CC or1k-linux-user/tcg/tcg-op.o
CC mipsn32-linux-user/linux-user/syscall.o
CC mipsn32el-linux-user/linux-user/signal.o
CC mipsn32el-linux-user/linux-user/elfload.o
CC mipsn32el-linux-user/linux-user/linuxload.o
CC mipsn32el-linux-user/linux-user/uaccess.o
CC mipsn32el-linux-user/linux-user/uname.o
CC or1k-linux-user/tcg/optimize.o
CC nios2-linux-user/linux-user/strace.o
CCAS mipsn32el-linux-user/linux-user/safe-syscall.o
CC mipsn32el-linux-user/target/mips/translate.o
CC nios2-linux-user/linux-user/mmap.o
CC or1k-linux-user/tcg/tcg-common.o
CC mipsn32-linux-user/linux-user/strace.o
CC nios2-linux-user/linux-user/signal.o
CC or1k-linux-user/fpu/softfloat.o
CC nios2-linux-user/linux-user/elfload.o
CC mipsn32-linux-user/linux-user/mmap.o
CC mipsn32-linux-user/linux-user/signal.o
CC nios2-linux-user/linux-user/linuxload.o
CC mipsn32-linux-user/linux-user/elfload.o
CC nios2-linux-user/linux-user/uaccess.o
CC nios2-linux-user/linux-user/uname.o
CC mipsn32-linux-user/linux-user/linuxload.o
CC or1k-linux-user/disas.o
CCAS nios2-linux-user/linux-user/safe-syscall.o
CC nios2-linux-user/target/nios2/translate.o
CC or1k-linux-user/tcg-runtime.o
CC mipsn32-linux-user/linux-user/uaccess.o
CC nios2-linux-user/target/nios2/op_helper.o
CC mipsn32-linux-user/linux-user/uname.o
CC nios2-linux-user/target/nios2/helper.o
CC or1k-linux-user/hax-stub.o
CCAS mipsn32-linux-user/linux-user/safe-syscall.o
CC mipsn32-linux-user/target/mips/translate.o
CC nios2-linux-user/target/nios2/cpu.o
CC or1k-linux-user/kvm-stub.o
CC mipsn32el-linux-user/target/mips/dsp_helper.o
CC or1k-linux-user/gdbstub.o
CC nios2-linux-user/target/nios2/mmu.o
GEN trace/generated-helpers.c
CC nios2-linux-user/trace/control-target.o
CC or1k-linux-user/thunk.o
CC nios2-linux-user/trace/generated-helpers.o
CC mipsn32el-linux-user/target/mips/op_helper.o
LINK nios2-linux-user/qemu-nios2
CC or1k-linux-user/user-exec.o
CC or1k-linux-user/user-exec-stub.o
GEN ppc64abi32-linux-user/config-target.h
CC ppc64abi32-linux-user/exec.o
CC or1k-linux-user/linux-user/main.o
CC or1k-linux-user/linux-user/syscall.o
CC ppc64abi32-linux-user/translate-all.o
CC ppc64abi32-linux-user/cpu-exec.o
CC ppc64abi32-linux-user/translate-common.o
CC mipsn32el-linux-user/target/mips/lmi_helper.o
CC ppc64abi32-linux-user/cpu-exec-common.o
CC ppc64abi32-linux-user/tcg/tcg.o
CC mipsn32el-linux-user/target/mips/helper.o
CC mipsn32el-linux-user/target/mips/cpu.o
CC mipsn32el-linux-user/target/mips/gdbstub.o
CC mipsn32-linux-user/target/mips/dsp_helper.o
CC or1k-linux-user/linux-user/strace.o
CC mipsn32el-linux-user/target/mips/msa_helper.o
CC ppc64abi32-linux-user/tcg/tcg-op.o
CC or1k-linux-user/linux-user/mmap.o
CC mipsn32-linux-user/target/mips/op_helper.o
CC or1k-linux-user/linux-user/signal.o
CC or1k-linux-user/linux-user/elfload.o
CC or1k-linux-user/linux-user/linuxload.o
CC ppc64abi32-linux-user/tcg/optimize.o
CC or1k-linux-user/linux-user/uaccess.o
CC or1k-linux-user/linux-user/uname.o
CCAS or1k-linux-user/linux-user/safe-syscall.o
CC mipsn32-linux-user/target/mips/lmi_helper.o
CC or1k-linux-user/target/openrisc/cpu.o
CC or1k-linux-user/target/openrisc/exception.o
CC ppc64abi32-linux-user/tcg/tcg-common.o
CC mipsn32-linux-user/target/mips/helper.o
CC ppc64abi32-linux-user/fpu/softfloat.o
CC or1k-linux-user/target/openrisc/interrupt.o
CC mipsn32-linux-user/target/mips/cpu.o
CC or1k-linux-user/target/openrisc/mmu.o
CC mipsn32el-linux-user/target/mips/mips-semi.o
CC mipsn32-linux-user/target/mips/gdbstub.o
CC or1k-linux-user/target/openrisc/translate.o
GEN trace/generated-helpers.c
CC mipsn32el-linux-user/trace/control-target.o
CC mipsn32-linux-user/target/mips/msa_helper.o
CC mipsn32el-linux-user/trace/generated-helpers.o
CC or1k-linux-user/target/openrisc/exception_helper.o
LINK mipsn32el-linux-user/qemu-mipsn32el
CC or1k-linux-user/target/openrisc/fpu_helper.o
CC mipsn32-linux-user/target/mips/mips-semi.o
CC or1k-linux-user/target/openrisc/interrupt_helper.o
CC ppc64abi32-linux-user/disas.o
CC or1k-linux-user/target/openrisc/mmu_helper.o
GEN ppc64le-linux-user/config-target.h
CC ppc64abi32-linux-user/tcg-runtime.o
CC or1k-linux-user/target/openrisc/sys_helper.o
CC ppc64le-linux-user/exec.o
CC or1k-linux-user/target/openrisc/gdbstub.o
GEN ppc64abi32-linux-user/gdbstub-xml.c
CC ppc64le-linux-user/translate-all.o
GEN trace/generated-helpers.c
CC or1k-linux-user/trace/control-target.o
CC or1k-linux-user/trace/generated-helpers.o
CC ppc64le-linux-user/cpu-exec.o
LINK or1k-linux-user/qemu-or1k
CC ppc64abi32-linux-user/hax-stub.o
CC ppc64le-linux-user/translate-common.o
GEN trace/generated-helpers.c
CC mipsn32-linux-user/trace/control-target.o
CC ppc64abi32-linux-user/kvm-stub.o
CC ppc64abi32-linux-user/libdecnumber/decContext.o
CC ppc64le-linux-user/cpu-exec-common.o
CC ppc64abi32-linux-user/libdecnumber/decNumber.o
CC mipsn32-linux-user/trace/generated-helpers.o
CC ppc64le-linux-user/tcg/tcg.o
LINK mipsn32-linux-user/qemu-mipsn32
GEN ppc64-linux-user/config-target.h
CC ppc64-linux-user/exec.o
CC ppc64-linux-user/translate-all.o
CC ppc64abi32-linux-user/libdecnumber/dpd/decimal32.o
CC ppc64-linux-user/cpu-exec.o
CC ppc64abi32-linux-user/libdecnumber/dpd/decimal64.o
GEN ppc-linux-user/config-target.h
CC ppc64-linux-user/translate-common.o
CC ppc-linux-user/exec.o
CC ppc64abi32-linux-user/libdecnumber/dpd/decimal128.o
CC ppc-linux-user/translate-all.o
CC ppc64le-linux-user/tcg/tcg-op.o
CC ppc64-linux-user/cpu-exec-common.o
CC ppc64abi32-linux-user/gdbstub.o
CC ppc64-linux-user/tcg/tcg.o
CC ppc-linux-user/cpu-exec.o
CC ppc64abi32-linux-user/thunk.o
CC ppc-linux-user/translate-common.o
CC ppc64abi32-linux-user/user-exec.o
CC ppc-linux-user/cpu-exec-common.o
CC ppc64abi32-linux-user/user-exec-stub.o
CC ppc-linux-user/tcg/tcg.o
CC ppc64abi32-linux-user/linux-user/main.o
CC ppc64abi32-linux-user/linux-user/syscall.o
CC ppc64le-linux-user/tcg/optimize.o
CC ppc64-linux-user/tcg/tcg-op.o
CC ppc-linux-user/tcg/tcg-op.o
CC ppc64le-linux-user/tcg/tcg-common.o
CC ppc64le-linux-user/fpu/softfloat.o
CC ppc64-linux-user/tcg/optimize.o
CC ppc-linux-user/tcg/optimize.o
CC ppc64abi32-linux-user/linux-user/strace.o
CC ppc64-linux-user/tcg/tcg-common.o
CC ppc64abi32-linux-user/linux-user/mmap.o
CC ppc-linux-user/tcg/tcg-common.o
CC ppc64le-linux-user/disas.o
CC ppc64-linux-user/fpu/softfloat.o
CC ppc-linux-user/fpu/softfloat.o
CC ppc64abi32-linux-user/linux-user/signal.o
CC ppc64le-linux-user/tcg-runtime.o
CC ppc64abi32-linux-user/linux-user/elfload.o
GEN ppc64le-linux-user/gdbstub-xml.c
CC ppc64abi32-linux-user/linux-user/linuxload.o
CC ppc64le-linux-user/hax-stub.o
CC ppc64abi32-linux-user/linux-user/uaccess.o
CC ppc64abi32-linux-user/linux-user/uname.o
CC ppc64le-linux-user/kvm-stub.o
CC ppc-linux-user/disas.o
CCAS ppc64abi32-linux-user/linux-user/safe-syscall.o
CC ppc64le-linux-user/libdecnumber/decContext.o
CC ppc64abi32-linux-user/target/ppc/cpu-models.o
CC ppc-linux-user/tcg-runtime.o
CC ppc64-linux-user/disas.o
CC ppc64le-linux-user/libdecnumber/decNumber.o
CC ppc64-linux-user/tcg-runtime.o
GEN ppc-linux-user/gdbstub-xml.c
GEN ppc64-linux-user/gdbstub-xml.c
CC ppc64abi32-linux-user/target/ppc/translate.o
CC ppc-linux-user/hax-stub.o
CC ppc64le-linux-user/libdecnumber/dpd/decimal32.o
CC ppc-linux-user/kvm-stub.o
CC ppc-linux-user/libdecnumber/decContext.o
CC ppc-linux-user/libdecnumber/decNumber.o
CC ppc64-linux-user/hax-stub.o
CC ppc64le-linux-user/libdecnumber/dpd/decimal64.o
CC ppc64-linux-user/kvm-stub.o
CC ppc64le-linux-user/libdecnumber/dpd/decimal128.o
CC ppc64-linux-user/libdecnumber/decContext.o
CC ppc64le-linux-user/gdbstub.o
CC ppc64-linux-user/libdecnumber/decNumber.o
CC ppc-linux-user/libdecnumber/dpd/decimal32.o
CC ppc-linux-user/libdecnumber/dpd/decimal64.o
CC ppc64le-linux-user/thunk.o
CC ppc-linux-user/libdecnumber/dpd/decimal128.o
CC ppc64le-linux-user/user-exec.o
CC ppc-linux-user/gdbstub.o
CC ppc64-linux-user/libdecnumber/dpd/decimal32.o
CC ppc64le-linux-user/user-exec-stub.o
CC ppc64-linux-user/libdecnumber/dpd/decimal64.o
CC ppc-linux-user/thunk.o
CC ppc64le-linux-user/linux-user/main.o
CC ppc-linux-user/user-exec.o
CC ppc64-linux-user/libdecnumber/dpd/decimal128.o
CC ppc-linux-user/user-exec-stub.o
CC ppc64-linux-user/gdbstub.o
CC ppc64le-linux-user/linux-user/syscall.o
CC ppc-linux-user/linux-user/main.o
CC ppc64-linux-user/thunk.o
CC ppc-linux-user/linux-user/syscall.o
CC ppc64-linux-user/user-exec.o
CC ppc64-linux-user/user-exec-stub.o
CC ppc64-linux-user/linux-user/main.o
CC ppc64-linux-user/linux-user/syscall.o
CC ppc64le-linux-user/linux-user/strace.o
CC ppc64le-linux-user/linux-user/mmap.o
CC ppc-linux-user/linux-user/strace.o
CC ppc64le-linux-user/linux-user/signal.o
CC ppc64-linux-user/linux-user/strace.o
CC ppc-linux-user/linux-user/mmap.o
CC ppc64le-linux-user/linux-user/elfload.o
CC ppc-linux-user/linux-user/signal.o
CC ppc64-linux-user/linux-user/mmap.o
CC ppc64le-linux-user/linux-user/linuxload.o
CC ppc64abi32-linux-user/target/ppc/kvm-stub.o
CC ppc64-linux-user/linux-user/signal.o
CC ppc64abi32-linux-user/target/ppc/dfp_helper.o
CC ppc-linux-user/linux-user/elfload.o
CC ppc64le-linux-user/linux-user/uaccess.o
CC ppc64-linux-user/linux-user/elfload.o
CC ppc64le-linux-user/linux-user/uname.o
CCAS ppc64le-linux-user/linux-user/safe-syscall.o
CC ppc64le-linux-user/target/ppc/cpu-models.o
CC ppc64-linux-user/linux-user/linuxload.o
CC ppc-linux-user/linux-user/linuxload.o
CC ppc64abi32-linux-user/target/ppc/excp_helper.o
CC ppc64-linux-user/linux-user/uaccess.o
CC ppc-linux-user/linux-user/uaccess.o
CC ppc64abi32-linux-user/target/ppc/fpu_helper.o
CC ppc-linux-user/linux-user/uname.o
CC ppc64-linux-user/linux-user/uname.o
CCAS ppc-linux-user/linux-user/safe-syscall.o
CCAS ppc64-linux-user/linux-user/safe-syscall.o
CC ppc-linux-user/target/ppc/cpu-models.o
CC ppc64-linux-user/target/ppc/cpu-models.o
CC ppc64le-linux-user/target/ppc/translate.o
CC ppc-linux-user/target/ppc/translate.o
CC ppc64-linux-user/target/ppc/translate.o
CC ppc64abi32-linux-user/target/ppc/int_helper.o
CC ppc64abi32-linux-user/target/ppc/timebase_helper.o
CC ppc64abi32-linux-user/target/ppc/misc_helper.o
CC ppc64abi32-linux-user/target/ppc/mem_helper.o
CC ppc64abi32-linux-user/target/ppc/user_only_helper.o
CC ppc64abi32-linux-user/target/ppc/gdbstub.o
GEN trace/generated-helpers.c
CC ppc64abi32-linux-user/trace/control-target.o
CC ppc64abi32-linux-user/gdbstub-xml.o
CC ppc64abi32-linux-user/trace/generated-helpers.o
LINK ppc64abi32-linux-user/qemu-ppc64abi32
CC ppc-linux-user/target/ppc/kvm-stub.o
CC ppc-linux-user/target/ppc/dfp_helper.o
CC ppc64-linux-user/target/ppc/kvm-stub.o
CC ppc64-linux-user/target/ppc/dfp_helper.o
CC ppc64le-linux-user/target/ppc/kvm-stub.o
CC ppc-linux-user/target/ppc/excp_helper.o
CC ppc64le-linux-user/target/ppc/dfp_helper.o
CC ppc-linux-user/target/ppc/fpu_helper.o
CC ppc-linux-user/target/ppc/int_helper.o
CC ppc64le-linux-user/target/ppc/excp_helper.o
CC ppc64le-linux-user/target/ppc/fpu_helper.o
CC ppc64-linux-user/target/ppc/excp_helper.o
CC ppc-linux-user/target/ppc/timebase_helper.o
CC ppc64-linux-user/target/ppc/fpu_helper.o
CC ppc64le-linux-user/target/ppc/int_helper.o
CC ppc64le-linux-user/target/ppc/timebase_helper.o
CC ppc64le-linux-user/target/ppc/misc_helper.o
CC ppc-linux-user/target/ppc/misc_helper.o
CC ppc64le-linux-user/target/ppc/mem_helper.o
CC ppc-linux-user/target/ppc/mem_helper.o
CC ppc64le-linux-user/target/ppc/user_only_helper.o
CC ppc64le-linux-user/target/ppc/gdbstub.o
GEN trace/generated-helpers.c
CC ppc-linux-user/target/ppc/user_only_helper.o
CC ppc64le-linux-user/trace/control-target.o
CC ppc-linux-user/target/ppc/gdbstub.o
CC ppc64-linux-user/target/ppc/int_helper.o
CC ppc64le-linux-user/gdbstub-xml.o
GEN trace/generated-helpers.c
CC ppc-linux-user/trace/control-target.o
CC ppc64le-linux-user/trace/generated-helpers.o
CC ppc-linux-user/gdbstub-xml.o
LINK ppc64le-linux-user/qemu-ppc64le
CC ppc-linux-user/trace/generated-helpers.o
CC s390x-linux-user/gen-features
GEN s390x-linux-user/config-target.h
GEN s390x-linux-user/gen-features.h
CC s390x-linux-user/exec.o
LINK ppc-linux-user/qemu-ppc
CC ppc64-linux-user/target/ppc/timebase_helper.o
CC s390x-linux-user/translate-all.o
CC ppc64-linux-user/target/ppc/misc_helper.o
CC ppc64-linux-user/target/ppc/mem_helper.o
GEN sh4eb-linux-user/config-target.h
CC s390x-linux-user/cpu-exec.o
CC sh4eb-linux-user/exec.o
CC ppc64-linux-user/target/ppc/user_only_helper.o
GEN sh4-linux-user/config-target.h
CC sh4-linux-user/exec.o
CC ppc64-linux-user/target/ppc/gdbstub.o
CC s390x-linux-user/translate-common.o
CC sh4eb-linux-user/translate-all.o
CC sh4-linux-user/translate-all.o
CC s390x-linux-user/cpu-exec-common.o
GEN trace/generated-helpers.c
CC ppc64-linux-user/trace/control-target.o
CC s390x-linux-user/tcg/tcg.o
CC sh4eb-linux-user/cpu-exec.o
CC ppc64-linux-user/gdbstub-xml.o
CC sh4eb-linux-user/translate-common.o
CC sh4-linux-user/cpu-exec.o
CC sh4eb-linux-user/cpu-exec-common.o
CC ppc64-linux-user/trace/generated-helpers.o
CC sh4eb-linux-user/tcg/tcg.o
CC sh4-linux-user/translate-common.o
LINK ppc64-linux-user/qemu-ppc64
CC sh4-linux-user/cpu-exec-common.o
CC s390x-linux-user/tcg/tcg-op.o
CC sh4-linux-user/tcg/tcg.o
CC s390x-linux-user/tcg/optimize.o
CC s390x-linux-user/tcg/tcg-common.o
CC sh4eb-linux-user/tcg/tcg-op.o
CC s390x-linux-user/fpu/softfloat.o
CC sh4-linux-user/tcg/tcg-op.o
CC s390x-linux-user/disas.o
CC s390x-linux-user/tcg-runtime.o
GEN s390x-linux-user/gdbstub-xml.c
CC sh4eb-linux-user/tcg/optimize.o
CC sh4-linux-user/tcg/optimize.o
CC s390x-linux-user/hax-stub.o
CC s390x-linux-user/kvm-stub.o
CC s390x-linux-user/gdbstub.o
CC sh4eb-linux-user/tcg/tcg-common.o
CC s390x-linux-user/thunk.o
CC s390x-linux-user/user-exec.o
CC sh4eb-linux-user/fpu/softfloat.o
CC sh4-linux-user/tcg/tcg-common.o
CC s390x-linux-user/user-exec-stub.o
CC sh4-linux-user/fpu/softfloat.o
CC s390x-linux-user/linux-user/main.o
CC sh4-linux-user/disas.o
CC sh4-linux-user/tcg-runtime.o
CC s390x-linux-user/linux-user/syscall.o
CC sh4-linux-user/hax-stub.o
CC sh4-linux-user/kvm-stub.o
CC sh4-linux-user/gdbstub.o
CC sh4eb-linux-user/disas.o
CC sh4-linux-user/thunk.o
CC sh4eb-linux-user/tcg-runtime.o
CC sh4-linux-user/user-exec.o
CC sh4-linux-user/user-exec-stub.o
CC s390x-linux-user/linux-user/strace.o
CC sh4-linux-user/linux-user/main.o
CC sh4eb-linux-user/hax-stub.o
CC sh4eb-linux-user/kvm-stub.o
CC sh4-linux-user/linux-user/syscall.o
CC s390x-linux-user/linux-user/mmap.o
CC s390x-linux-user/linux-user/signal.o
CC sh4eb-linux-user/gdbstub.o
CC sh4eb-linux-user/thunk.o
CC s390x-linux-user/linux-user/elfload.o
CC s390x-linux-user/linux-user/linuxload.o
CC sh4eb-linux-user/user-exec.o
CC sh4eb-linux-user/user-exec-stub.o
GEN sparc32plus-linux-user/config-target.h
CC sh4eb-linux-user/linux-user/main.o
CC sparc32plus-linux-user/exec.o
CC s390x-linux-user/linux-user/uaccess.o
CC sh4eb-linux-user/linux-user/syscall.o
CC sparc32plus-linux-user/translate-all.o
CC s390x-linux-user/linux-user/uname.o
CC sparc32plus-linux-user/cpu-exec.o
CCAS s390x-linux-user/linux-user/safe-syscall.o
CC s390x-linux-user/target/s390x/translate.o
CC sparc32plus-linux-user/translate-common.o
CC sparc32plus-linux-user/cpu-exec-common.o
CC sparc32plus-linux-user/tcg/tcg.o
CC sh4-linux-user/linux-user/strace.o
CC sh4-linux-user/linux-user/mmap.o
CC sparc32plus-linux-user/tcg/tcg-op.o
CC s390x-linux-user/target/s390x/helper.o
CC sh4-linux-user/linux-user/signal.o
CC s390x-linux-user/target/s390x/cpu.o
CC s390x-linux-user/target/s390x/interrupt.o
CC sh4eb-linux-user/linux-user/strace.o
CC sh4-linux-user/linux-user/elfload.o
CC s390x-linux-user/target/s390x/int_helper.o
CC s390x-linux-user/target/s390x/fpu_helper.o
CC sh4-linux-user/linux-user/linuxload.o
CC sh4eb-linux-user/linux-user/mmap.o
CC sh4-linux-user/linux-user/uaccess.o
CC s390x-linux-user/target/s390x/cc_helper.o
CC sh4-linux-user/linux-user/uname.o
CC sh4eb-linux-user/linux-user/signal.o
CC s390x-linux-user/target/s390x/mem_helper.o
CC sparc32plus-linux-user/tcg/optimize.o
CCAS sh4-linux-user/linux-user/safe-syscall.o
CC sh4-linux-user/linux-user/flatload.o
CC sh4eb-linux-user/linux-user/elfload.o
CC s390x-linux-user/target/s390x/misc_helper.o
CC sh4-linux-user/target/sh4/translate.o
CC sparc32plus-linux-user/tcg/tcg-common.o
CC s390x-linux-user/target/s390x/gdbstub.o
CC sparc32plus-linux-user/fpu/softfloat.o
CC sh4eb-linux-user/linux-user/linuxload.o
CC s390x-linux-user/target/s390x/cpu_models.o
CC sh4eb-linux-user/linux-user/uaccess.o
CC s390x-linux-user/target/s390x/cpu_features.o
CC sh4eb-linux-user/linux-user/uname.o
GEN trace/generated-helpers.c
CC s390x-linux-user/trace/control-target.o
CCAS sh4eb-linux-user/linux-user/safe-syscall.o
CC s390x-linux-user/gdbstub-xml.o
CC sh4eb-linux-user/linux-user/flatload.o
CC s390x-linux-user/trace/generated-helpers.o
CC sh4-linux-user/target/sh4/op_helper.o
CC sh4eb-linux-user/target/sh4/translate.o
LINK s390x-linux-user/qemu-s390x
CC sh4-linux-user/target/sh4/helper.o
CC sparc32plus-linux-user/disas.o
CC sh4-linux-user/target/sh4/cpu.o
CC sh4-linux-user/target/sh4/gdbstub.o
GEN sparc64-linux-user/config-target.h
CC sparc32plus-linux-user/tcg-runtime.o
GEN trace/generated-helpers.c
CC sparc64-linux-user/exec.o
CC sh4-linux-user/trace/control-target.o
CC sparc64-linux-user/translate-all.o
CC sh4-linux-user/trace/generated-helpers.o
CC sparc32plus-linux-user/hax-stub.o
CC sparc64-linux-user/cpu-exec.o
LINK sh4-linux-user/qemu-sh4
CC sparc32plus-linux-user/kvm-stub.o
CC sh4eb-linux-user/target/sh4/op_helper.o
CC sparc32plus-linux-user/gdbstub.o
CC sh4eb-linux-user/target/sh4/helper.o
CC sparc64-linux-user/translate-common.o
CC sh4eb-linux-user/target/sh4/cpu.o
CC sh4eb-linux-user/target/sh4/gdbstub.o
CC sparc64-linux-user/cpu-exec-common.o
GEN sparc-linux-user/config-target.h
CC sparc-linux-user/exec.o
GEN trace/generated-helpers.c
CC sparc32plus-linux-user/thunk.o
CC sh4eb-linux-user/trace/control-target.o
CC sparc64-linux-user/tcg/tcg.o
CC sparc32plus-linux-user/user-exec.o
CC sh4eb-linux-user/trace/generated-helpers.o
CC sparc-linux-user/translate-all.o
LINK sh4eb-linux-user/qemu-sh4eb
CC sparc32plus-linux-user/user-exec-stub.o
CC sparc-linux-user/cpu-exec.o
CC sparc32plus-linux-user/linux-user/main.o
GEN tilegx-linux-user/config-target.h
CC tilegx-linux-user/exec.o
CC sparc-linux-user/translate-common.o
CC sparc-linux-user/cpu-exec-common.o
CC tilegx-linux-user/translate-all.o
CC sparc32plus-linux-user/linux-user/syscall.o
CC sparc64-linux-user/tcg/tcg-op.o
CC sparc-linux-user/tcg/tcg.o
CC tilegx-linux-user/cpu-exec.o
CC tilegx-linux-user/translate-common.o
CC tilegx-linux-user/cpu-exec-common.o
CC tilegx-linux-user/tcg/tcg.o
CC sparc64-linux-user/tcg/optimize.o
CC sparc-linux-user/tcg/tcg-op.o
CC sparc64-linux-user/tcg/tcg-common.o
CC sparc64-linux-user/fpu/softfloat.o
CC tilegx-linux-user/tcg/tcg-op.o
CC sparc32plus-linux-user/linux-user/strace.o
CC sparc32plus-linux-user/linux-user/mmap.o
CC sparc-linux-user/tcg/optimize.o
CC sparc32plus-linux-user/linux-user/signal.o
CC sparc-linux-user/tcg/tcg-common.o
CC sparc32plus-linux-user/linux-user/elfload.o
CC sparc-linux-user/fpu/softfloat.o
CC tilegx-linux-user/tcg/optimize.o
CC sparc32plus-linux-user/linux-user/linuxload.o
CC sparc64-linux-user/disas.o
CC sparc32plus-linux-user/linux-user/uaccess.o
CC tilegx-linux-user/tcg/tcg-common.o
CC sparc32plus-linux-user/linux-user/uname.o
CC sparc64-linux-user/tcg-runtime.o
CC tilegx-linux-user/fpu/softfloat.o
CCAS sparc32plus-linux-user/linux-user/safe-syscall.o
CC sparc32plus-linux-user/target/sparc/translate.o
CC sparc64-linux-user/hax-stub.o
CC sparc64-linux-user/kvm-stub.o
CC sparc64-linux-user/gdbstub.o
CC sparc-linux-user/disas.o
CC sparc-linux-user/tcg-runtime.o
CC sparc64-linux-user/thunk.o
CC tilegx-linux-user/disas.o
CC sparc64-linux-user/user-exec.o
CC tilegx-linux-user/tcg-runtime.o
CC sparc-linux-user/hax-stub.o
CC sparc32plus-linux-user/target/sparc/helper.o
CC sparc64-linux-user/user-exec-stub.o
CC sparc32plus-linux-user/target/sparc/cpu.o
CC sparc-linux-user/kvm-stub.o
CC tilegx-linux-user/hax-stub.o
CC sparc-linux-user/gdbstub.o
CC sparc64-linux-user/linux-user/main.o
CC tilegx-linux-user/kvm-stub.o
CC sparc32plus-linux-user/target/sparc/fop_helper.o
CC sparc64-linux-user/linux-user/syscall.o
CC sparc-linux-user/thunk.o
CC tilegx-linux-user/gdbstub.o
CC sparc32plus-linux-user/target/sparc/cc_helper.o
CC sparc-linux-user/user-exec.o
CC sparc32plus-linux-user/target/sparc/win_helper.o
CC sparc-linux-user/user-exec-stub.o
CC tilegx-linux-user/thunk.o
CC sparc-linux-user/linux-user/main.o
CC sparc32plus-linux-user/target/sparc/mmu_helper.o
CC sparc-linux-user/linux-user/syscall.o
CC tilegx-linux-user/user-exec.o
CC sparc32plus-linux-user/target/sparc/ldst_helper.o
CC tilegx-linux-user/user-exec-stub.o
CC sparc32plus-linux-user/target/sparc/int64_helper.o
CC tilegx-linux-user/linux-user/main.o
CC sparc32plus-linux-user/target/sparc/vis_helper.o
CC tilegx-linux-user/linux-user/syscall.o
CC sparc32plus-linux-user/target/sparc/gdbstub.o
GEN trace/generated-helpers.c
CC sparc32plus-linux-user/trace/control-target.o
CC sparc64-linux-user/linux-user/strace.o
CC sparc32plus-linux-user/trace/generated-helpers.o
CC sparc64-linux-user/linux-user/mmap.o
LINK sparc32plus-linux-user/qemu-sparc32plus
CC sparc64-linux-user/linux-user/signal.o
CC tilegx-linux-user/linux-user/strace.o
CC sparc-linux-user/linux-user/strace.o
CC sparc64-linux-user/linux-user/elfload.o
CC sparc-linux-user/linux-user/mmap.o
CC tilegx-linux-user/linux-user/mmap.o
CC sparc-linux-user/linux-user/signal.o
CC sparc64-linux-user/linux-user/linuxload.o
CC sparc-linux-user/linux-user/elfload.o
CC sparc64-linux-user/linux-user/uaccess.o
CC tilegx-linux-user/linux-user/signal.o
CC sparc-linux-user/linux-user/linuxload.o
CC sparc64-linux-user/linux-user/uname.o
CC tilegx-linux-user/linux-user/elfload.o
CC sparc-linux-user/linux-user/uaccess.o
CCAS sparc64-linux-user/linux-user/safe-syscall.o
CC sparc-linux-user/linux-user/uname.o
CC sparc64-linux-user/target/sparc/translate.o
CC tilegx-linux-user/linux-user/linuxload.o
CCAS sparc-linux-user/linux-user/safe-syscall.o
CC tilegx-linux-user/linux-user/uaccess.o
CC sparc-linux-user/target/sparc/translate.o
CC sparc-linux-user/target/sparc/helper.o
CC tilegx-linux-user/linux-user/uname.o
CCAS tilegx-linux-user/linux-user/safe-syscall.o
CC tilegx-linux-user/target/tilegx/cpu.o
CC sparc-linux-user/target/sparc/cpu.o
CC tilegx-linux-user/target/tilegx/translate.o
CC tilegx-linux-user/target/tilegx/helper.o
CC sparc-linux-user/target/sparc/fop_helper.o
CC sparc-linux-user/target/sparc/cc_helper.o
CC sparc64-linux-user/target/sparc/helper.o
CC tilegx-linux-user/target/tilegx/simd_helper.o
CC sparc-linux-user/target/sparc/win_helper.o
CC sparc-linux-user/target/sparc/mmu_helper.o
CC sparc64-linux-user/target/sparc/cpu.o
GEN trace/generated-helpers.c
CC tilegx-linux-user/trace/control-target.o
CC sparc-linux-user/target/sparc/ldst_helper.o
CC sparc64-linux-user/target/sparc/fop_helper.o
CC tilegx-linux-user/trace/generated-helpers.o
GEN x86_64-linux-user/config-target.h
CC x86_64-linux-user/exec.o
CC sparc-linux-user/target/sparc/int32_helper.o
CC sparc64-linux-user/target/sparc/cc_helper.o
LINK tilegx-linux-user/qemu-tilegx
CC sparc-linux-user/target/sparc/gdbstub.o
CC x86_64-linux-user/translate-all.o
CC sparc64-linux-user/target/sparc/win_helper.o
GEN trace/generated-helpers.c
CC sparc-linux-user/trace/control-target.o
CC x86_64-linux-user/cpu-exec.o
CC sparc64-linux-user/target/sparc/mmu_helper.o
CC sparc-linux-user/trace/generated-helpers.o
CC x86_64-linux-user/translate-common.o
CC sparc64-linux-user/target/sparc/ldst_helper.o
CC x86_64-linux-user/cpu-exec-common.o
LINK sparc-linux-user/qemu-sparc
CC sparc64-linux-user/target/sparc/int64_helper.o
CC sparc64-linux-user/target/sparc/vis_helper.o
CC x86_64-linux-user/tcg/tcg.o
CC sparc64-linux-user/target/sparc/gdbstub.o
CC x86_64-linux-user/tcg/tcg-op.o
CC x86_64-linux-user/tcg/optimize.o
GEN trace/generated-helpers.c
CC sparc64-linux-user/trace/control-target.o
CC sparc64-linux-user/trace/generated-helpers.o
CC x86_64-linux-user/tcg/tcg-common.o
LINK sparc64-linux-user/qemu-sparc64
CC x86_64-linux-user/fpu/softfloat.o
CC x86_64-linux-user/disas.o
CC x86_64-linux-user/tcg-runtime.o
CC x86_64-linux-user/hax-stub.o
CC x86_64-linux-user/kvm-stub.o
CC x86_64-linux-user/gdbstub.o
CC x86_64-linux-user/thunk.o
CC x86_64-linux-user/user-exec.o
CC x86_64-linux-user/user-exec-stub.o
CC x86_64-linux-user/linux-user/main.o
CC x86_64-linux-user/linux-user/syscall.o
CC x86_64-linux-user/linux-user/strace.o
CC x86_64-linux-user/linux-user/mmap.o
CC x86_64-linux-user/linux-user/signal.o
CC x86_64-linux-user/linux-user/elfload.o
CC x86_64-linux-user/linux-user/linuxload.o
CC x86_64-linux-user/linux-user/uaccess.o
CC x86_64-linux-user/linux-user/uname.o
CCAS x86_64-linux-user/linux-user/safe-syscall.o
CC x86_64-linux-user/target/i386/translate.o
CC x86_64-linux-user/target/i386/helper.o
CC x86_64-linux-user/target/i386/cpu.o
CC x86_64-linux-user/target/i386/bpt_helper.o
CC x86_64-linux-user/target/i386/excp_helper.o
CC x86_64-linux-user/target/i386/fpu_helper.o
CC x86_64-linux-user/target/i386/cc_helper.o
CC x86_64-linux-user/target/i386/int_helper.o
CC x86_64-linux-user/target/i386/svm_helper.o
CC x86_64-linux-user/target/i386/smm_helper.o
CC x86_64-linux-user/target/i386/misc_helper.o
CC x86_64-linux-user/target/i386/mem_helper.o
CC x86_64-linux-user/target/i386/seg_helper.o
CC x86_64-linux-user/target/i386/mpx_helper.o
CC x86_64-linux-user/target/i386/gdbstub.o
CC x86_64-linux-user/target/i386/kvm-stub.o
GEN trace/generated-helpers.c
CC x86_64-linux-user/trace/control-target.o
CC x86_64-linux-user/trace/generated-helpers.o
LINK x86_64-linux-user/qemu-x86_64
TEST tests/qapi-schema/alternate-array.out
TEST tests/qapi-schema/alternate-clash.out
TEST tests/qapi-schema/alternate-base.out
TEST tests/qapi-schema/alternate-any.out
TEST tests/qapi-schema/alternate-conflict-dict.out
TEST tests/qapi-schema/alternate-empty.out
TEST tests/qapi-schema/alternate-nested.out
TEST tests/qapi-schema/alternate-conflict-string.out
TEST tests/qapi-schema/alternate-unknown.out
TEST tests/qapi-schema/args-alternate.out
TEST tests/qapi-schema/args-any.out
TEST tests/qapi-schema/args-array-empty.out
TEST tests/qapi-schema/args-array-unknown.out
TEST tests/qapi-schema/args-bad-boxed.out
TEST tests/qapi-schema/args-boxed-anon.out
TEST tests/qapi-schema/args-boxed-empty.out
TEST tests/qapi-schema/args-boxed-string.out
TEST tests/qapi-schema/args-int.out
TEST tests/qapi-schema/args-invalid.out
TEST tests/qapi-schema/args-member-array-bad.out
TEST tests/qapi-schema/args-member-case.out
TEST tests/qapi-schema/args-member-unknown.out
TEST tests/qapi-schema/args-union.out
TEST tests/qapi-schema/args-name-clash.out
TEST tests/qapi-schema/args-unknown.out
TEST tests/qapi-schema/bad-base.out
TEST tests/qapi-schema/bad-data.out
TEST tests/qapi-schema/bad-ident.out
TEST tests/qapi-schema/bad-type-bool.out
TEST tests/qapi-schema/bad-type-dict.out
TEST tests/qapi-schema/bad-type-int.out
TEST tests/qapi-schema/base-cycle-direct.out
TEST tests/qapi-schema/base-cycle-indirect.out
TEST tests/qapi-schema/command-int.out
TEST tests/qapi-schema/doc-bad-args.out
TEST tests/qapi-schema/comments.out
TEST tests/qapi-schema/doc-bad-symbol.out
TEST tests/qapi-schema/doc-duplicated-arg.out
TEST tests/qapi-schema/doc-duplicated-return.out
TEST tests/qapi-schema/doc-duplicated-since.out
TEST tests/qapi-schema/doc-empty-arg.out
TEST tests/qapi-schema/doc-empty-section.out
TEST tests/qapi-schema/doc-empty-symbol.out
TEST tests/qapi-schema/doc-interleaved-section.out
TEST tests/qapi-schema/doc-invalid-end.out
TEST tests/qapi-schema/doc-invalid-end2.out
TEST tests/qapi-schema/doc-invalid-return.out
TEST tests/qapi-schema/doc-invalid-section.out
TEST tests/qapi-schema/doc-invalid-start.out
TEST tests/qapi-schema/doc-missing-colon.out
TEST tests/qapi-schema/doc-missing-expr.out
TEST tests/qapi-schema/doc-missing-space.out
TEST tests/qapi-schema/doc-optional.out
TEST tests/qapi-schema/double-data.out
TEST tests/qapi-schema/double-type.out
TEST tests/qapi-schema/duplicate-key.out
TEST tests/qapi-schema/empty.out
TEST tests/qapi-schema/enum-bad-name.out
TEST tests/qapi-schema/enum-bad-prefix.out
TEST tests/qapi-schema/enum-clash-member.out
TEST tests/qapi-schema/enum-dict-member.out
TEST tests/qapi-schema/enum-int-member.out
TEST tests/qapi-schema/enum-member-case.out
TEST tests/qapi-schema/enum-missing-data.out
TEST tests/qapi-schema/enum-wrong-data.out
TEST tests/qapi-schema/escape-outside-string.out
TEST tests/qapi-schema/escape-too-big.out
TEST tests/qapi-schema/escape-too-short.out
TEST tests/qapi-schema/event-boxed-empty.out
TEST tests/qapi-schema/event-case.out
TEST tests/qapi-schema/event-nest-struct.out
TEST tests/qapi-schema/flat-union-array-branch.out
TEST tests/qapi-schema/flat-union-bad-base.out
TEST tests/qapi-schema/flat-union-bad-discriminator.out
TEST tests/qapi-schema/flat-union-base-any.out
TEST tests/qapi-schema/flat-union-base-union.out
TEST tests/qapi-schema/flat-union-clash-member.out
TEST tests/qapi-schema/flat-union-empty.out
TEST tests/qapi-schema/flat-union-incomplete-branch.out
TEST tests/qapi-schema/flat-union-inline.out
TEST tests/qapi-schema/flat-union-int-branch.out
TEST tests/qapi-schema/flat-union-invalid-branch-key.out
TEST tests/qapi-schema/flat-union-invalid-discriminator.out
TEST tests/qapi-schema/flat-union-no-base.out
TEST tests/qapi-schema/flat-union-optional-discriminator.out
TEST tests/qapi-schema/flat-union-string-discriminator.out
TEST tests/qapi-schema/funny-char.out
TEST tests/qapi-schema/ident-with-escape.out
TEST tests/qapi-schema/include-before-err.out
TEST tests/qapi-schema/include-cycle.out
TEST tests/qapi-schema/include-format-err.out
TEST tests/qapi-schema/include-nested-err.out
TEST tests/qapi-schema/include-no-file.out
TEST tests/qapi-schema/include-non-file.out
TEST tests/qapi-schema/include-relpath.out
TEST tests/qapi-schema/include-repetition.out
TEST tests/qapi-schema/include-self-cycle.out
TEST tests/qapi-schema/include-simple.out
TEST tests/qapi-schema/indented-expr.out
TEST tests/qapi-schema/leading-comma-list.out
TEST tests/qapi-schema/leading-comma-object.out
TEST tests/qapi-schema/missing-colon.out
TEST tests/qapi-schema/missing-comma-list.out
TEST tests/qapi-schema/missing-comma-object.out
TEST tests/qapi-schema/missing-type.out
TEST tests/qapi-schema/non-objects.out
TEST tests/qapi-schema/nested-struct-data.out
TEST tests/qapi-schema/qapi-schema-test.out
TEST tests/qapi-schema/quoted-structural-chars.out
TEST tests/qapi-schema/redefined-builtin.out
TEST tests/qapi-schema/redefined-command.out
TEST tests/qapi-schema/redefined-event.out
TEST tests/qapi-schema/redefined-type.out
TEST tests/qapi-schema/reserved-command-q.out
TEST tests/qapi-schema/reserved-enum-q.out
TEST tests/qapi-schema/reserved-member-has.out
TEST tests/qapi-schema/reserved-member-q.out
TEST tests/qapi-schema/reserved-member-u.out
TEST tests/qapi-schema/reserved-member-underscore.out
TEST tests/qapi-schema/reserved-type-kind.out
TEST tests/qapi-schema/reserved-type-list.out
TEST tests/qapi-schema/returns-alternate.out
TEST tests/qapi-schema/returns-array-bad.out
TEST tests/qapi-schema/returns-dict.out
TEST tests/qapi-schema/returns-unknown.out
TEST tests/qapi-schema/returns-whitelist.out
TEST tests/qapi-schema/struct-base-clash-deep.out
TEST tests/qapi-schema/struct-base-clash.out
TEST tests/qapi-schema/struct-data-invalid.out
TEST tests/qapi-schema/struct-member-invalid.out
TEST tests/qapi-schema/trailing-comma-list.out
TEST tests/qapi-schema/trailing-comma-object.out
TEST tests/qapi-schema/type-bypass-bad-gen.out
TEST tests/qapi-schema/unclosed-list.out
TEST tests/qapi-schema/unclosed-object.out
TEST tests/qapi-schema/unclosed-string.out
TEST tests/qapi-schema/unicode-str.out
TEST tests/qapi-schema/union-base-no-discriminator.out
TEST tests/qapi-schema/union-branch-case.out
TEST tests/qapi-schema/union-clash-branches.out
TEST tests/qapi-schema/union-empty.out
TEST tests/qapi-schema/union-invalid-base.out
TEST tests/qapi-schema/union-optional-branch.out
TEST tests/qapi-schema/union-unknown.out
TEST tests/qapi-schema/unknown-escape.out
CC tests/check-qdict.o
TEST tests/qapi-schema/unknown-expr-key.out
CC tests/test-char.o
CC tests/check-qfloat.o
CC tests/check-qint.o
CC tests/check-qstring.o
CC tests/check-qlist.o
CC tests/check-qnull.o
CC tests/check-qjson.o
CC tests/test-qobject-output-visitor.o
GEN tests/test-qapi-visit.c
GEN tests/test-qapi-types.c
GEN tests/test-qapi-event.c
GEN tests/test-qmp-introspect.c
CC tests/test-clone-visitor.o
CC tests/test-qobject-input-visitor.o
CC tests/test-qobject-input-strict.o
CC tests/test-qmp-commands.o
GEN tests/test-qmp-marshal.c
CC tests/test-string-input-visitor.o
CC tests/test-string-output-visitor.o
CC tests/test-qmp-event.o
CC tests/test-opts-visitor.o
CC tests/test-coroutine.o
CC tests/iothread.o
CC tests/test-visitor-serialization.o
CC tests/test-iov.o
CC tests/test-aio.o
CC tests/test-aio-multithread.o
CC tests/test-throttle.o
CC tests/test-thread-pool.o
CC tests/test-hbitmap.o
CC tests/test-blockjob.o
CC tests/test-blockjob-txn.o
CC tests/test-x86-cpuid.o
CC tests/test-xbzrle.o
CC tests/test-vmstate.o
CC tests/test-cutils.o
CC tests/test-shift128.o
CC tests/test-mul64.o
CC tests/test-int128.o
CC tests/rcutorture.o
CC tests/test-rcu-list.o
CC tests/test-qdist.o
CC tests/test-qht.o
CC tests/test-qht-par.o
CC tests/qht-bench.o
CC tests/test-bitops.o
CC tests/test-bitcnt.o
CC tests/test-qdev-global-props.o
CC tests/check-qom-interface.o
CC tests/check-qom-proplist.o
CC tests/test-qemu-opts.o
CC tests/test-write-threshold.o
CC tests/test-crypto-hmac.o
CC tests/test-crypto-hash.o
CC tests/test-crypto-cipher.o
CC tests/test-crypto-secret.o
CC tests/test-crypto-tlscredsx509.o
CC tests/crypto-tls-x509-helpers.o
CC tests/pkix_asn1_tab.o
CC tests/test-crypto-tlssession.o
CC tests/test-qga.o
CC tests/libqtest.o
CC tests/test-timed-average.o
CC tests/test-io-task.o
CC tests/test-io-channel-socket.o
CC tests/io-channel-helpers.o
CC tests/test-io-channel-file.o
CC tests/test-io-channel-tls.o
CC tests/test-io-channel-command.o
CC tests/test-io-channel-buffer.o
CC tests/test-base64.o
CC tests/test-crypto-pbkdf.o
CC tests/test-crypto-ivgen.o
CC tests/test-crypto-afsplit.o
CC tests/test-crypto-xts.o
CC tests/test-crypto-block.o
CC tests/test-logging.o
CC tests/test-replication.o
CC tests/test-bufferiszero.o
CC tests/test-uuid.o
CC tests/ptimer-test.o
CC tests/ptimer-test-stubs.o
CC tests/boot-serial-test.o
CC tests/libqos/pci.o
CC tests/libqos/fw_cfg.o
CC tests/libqos/malloc.o
CC tests/libqos/i2c.o
CC tests/libqos/libqos.o
CC tests/tmp105-test.o
CC tests/libqos/i2c-omap.o
CC tests/ds1338-test.o
CC tests/libqos/i2c-imx.o
CC tests/m25p80-test.o
CC tests/virtio-blk-test.o
CC tests/libqos/malloc-spapr.o
CC tests/libqos/libqos-spapr.o
CC tests/libqos/rtas.o
CC tests/libqos/pci-spapr.o
CC tests/libqos/malloc-pc.o
CC tests/libqos/pci-pc.o
CC tests/libqos/libqos-pc.o
CC tests/libqos/ahci.o
CC tests/libqos/virtio.o
CC tests/libqos/virtio-mmio.o
CC tests/libqos/virtio-pci.o
CC tests/libqos/malloc-generic.o
CC tests/test-arm-mptimer.o
CC tests/endianness-test.o
CC tests/fdc-test.o
CC tests/ide-test.o
CC tests/ahci-test.o
CC tests/boot-order-test.o
CC tests/hd-geo-test.o
CC tests/bios-tables-test.o
CC tests/boot-sector.o
CC tests/pxe-test.o
CC tests/rtc-test.o
CC tests/ipmi-kcs-test.o
CC tests/ipmi-bt-test.o
CC tests/i440fx-test.o
CC tests/fw_cfg-test.o
CC tests/drive_del-test.o
CC tests/wdt_ib700-test.o
CC tests/tco-test.o
CC tests/e1000-test.o
CC tests/e1000e-test.o
CC tests/rtl8139-test.o
CC tests/pcnet-test.o
CC tests/eepro100-test.o
CC tests/ne2000-test.o
CC tests/nvme-test.o
CC tests/ac97-test.o
CC tests/es1370-test.o
CC tests/virtio-net-test.o
CC tests/virtio-balloon-test.o
CC tests/virtio-rng-test.o
CC tests/virtio-scsi-test.o
CC tests/virtio-9p-test.o
CC tests/virtio-console-test.o
CC tests/virtio-serial-test.o
CC tests/tpci200-test.o
CC tests/ipoctal232-test.o
CC tests/display-vga-test.o
CC tests/intel-hda-test.o
CC tests/ivshmem-test.o
CC tests/vmxnet3-test.o
CC tests/i82801b11-test.o
CC tests/pvpanic-test.o
CC tests/ioh3420-test.o
CC tests/usb-hcd-ohci-test.o
CC tests/libqos/usb.o
CC tests/usb-hcd-uhci-test.o
CC tests/usb-hcd-ehci-test.o
CC tests/usb-hcd-xhci-test.o
CC tests/pc-cpu-test.o
CC tests/test-netfilter.o
CC tests/q35-test.o
CC tests/test-filter-mirror.o
CC tests/test-filter-redirector.o
CC tests/postcopy-test.o
CC tests/test-x86-cpuid-compat.o
CC tests/spapr-phb-test.o
CC tests/prom-env-test.o
CC tests/pnv-xscom-test.o
CC tests/rtas-test.o
CC tests/device-introspect-test.o
CC tests/qom-test.o
LINK tests/check-qdict
LINK tests/test-char
LINK tests/check-qfloat
LINK tests/check-qint
LINK tests/check-qstring
LINK tests/check-qlist
LINK tests/check-qnull
LINK tests/check-qjson
CC tests/test-qapi-visit.o
CC tests/test-qapi-types.o
CC tests/test-qapi-event.o
CC tests/test-qmp-introspect.o
CC tests/test-qmp-marshal.o
LINK tests/test-coroutine
LINK tests/test-iov
LINK tests/test-aio
LINK tests/test-aio-multithread
LINK tests/test-throttle
LINK tests/test-thread-pool
LINK tests/test-hbitmap
LINK tests/test-blockjob
LINK tests/test-x86-cpuid
LINK tests/test-blockjob-txn
LINK tests/test-xbzrle
LINK tests/test-vmstate
LINK tests/test-cutils
LINK tests/test-shift128
LINK tests/test-int128
LINK tests/test-mul64
LINK tests/rcutorture
LINK tests/test-rcu-list
LINK tests/test-qdist
LINK tests/test-qht
LINK tests/qht-bench
LINK tests/test-bitops
LINK tests/test-bitcnt
LINK tests/test-qdev-global-props
LINK tests/check-qom-interface
LINK tests/check-qom-proplist
LINK tests/test-qemu-opts
LINK tests/test-write-threshold
LINK tests/test-crypto-hash
LINK tests/test-crypto-hmac
LINK tests/test-crypto-cipher
LINK tests/test-crypto-secret
LINK tests/test-crypto-tlscredsx509
LINK tests/test-crypto-tlssession
LINK tests/test-qga
LINK tests/test-timed-average
LINK tests/test-io-task
LINK tests/test-io-channel-socket
LINK tests/test-io-channel-file
LINK tests/test-io-channel-tls
LINK tests/test-io-channel-command
LINK tests/test-io-channel-buffer
LINK tests/test-base64
LINK tests/test-crypto-pbkdf
LINK tests/test-crypto-ivgen
LINK tests/test-crypto-afsplit
LINK tests/test-crypto-xts
LINK tests/test-crypto-block
LINK tests/test-logging
LINK tests/test-replication
LINK tests/test-bufferiszero
LINK tests/test-uuid
LINK tests/ptimer-test
LINK tests/boot-serial-test
LINK tests/tmp105-test
LINK tests/ds1338-test
LINK tests/m25p80-test
LINK tests/virtio-blk-test
LINK tests/test-arm-mptimer
LINK tests/endianness-test
LINK tests/fdc-test
LINK tests/ide-test
LINK tests/ahci-test
LINK tests/hd-geo-test
LINK tests/boot-order-test
LINK tests/bios-tables-test
LINK tests/pxe-test
LINK tests/rtc-test
LINK tests/ipmi-kcs-test
LINK tests/ipmi-bt-test
LINK tests/i440fx-test
LINK tests/fw_cfg-test
LINK tests/drive_del-test
LINK tests/wdt_ib700-test
LINK tests/tco-test
LINK tests/e1000-test
LINK tests/e1000e-test
LINK tests/rtl8139-test
LINK tests/pcnet-test
LINK tests/eepro100-test
LINK tests/ne2000-test
LINK tests/nvme-test
LINK tests/ac97-test
LINK tests/es1370-test
LINK tests/virtio-net-test
LINK tests/virtio-balloon-test
LINK tests/virtio-rng-test
LINK tests/virtio-scsi-test
LINK tests/virtio-9p-test
LINK tests/virtio-serial-test
LINK tests/virtio-console-test
LINK tests/tpci200-test
LINK tests/display-vga-test
LINK tests/ipoctal232-test
LINK tests/ivshmem-test
LINK tests/intel-hda-test
LINK tests/vmxnet3-test
LINK tests/pvpanic-test
LINK tests/i82801b11-test
LINK tests/ioh3420-test
LINK tests/usb-hcd-ohci-test
LINK tests/usb-hcd-ehci-test
LINK tests/usb-hcd-uhci-test
LINK tests/usb-hcd-xhci-test
LINK tests/pc-cpu-test
LINK tests/q35-test
LINK tests/test-netfilter
LINK tests/test-filter-mirror
LINK tests/test-filter-redirector
LINK tests/postcopy-test
LINK tests/test-x86-cpuid-compat
LINK tests/spapr-phb-test
LINK tests/prom-env-test
LINK tests/pnv-xscom-test
LINK tests/rtas-test
LINK tests/qom-test
LINK tests/device-introspect-test
GTESTER tests/test-char
GTESTER tests/check-qdict
GTESTER tests/check-qfloat
GTESTER tests/check-qint
GTESTER tests/check-qstring
GTESTER tests/check-qlist
GTESTER tests/check-qnull
GTESTER tests/check-qjson
LINK tests/test-qobject-output-visitor
LINK tests/test-qobject-input-visitor
LINK tests/test-clone-visitor
LINK tests/test-qobject-input-strict
LINK tests/test-qmp-commands
LINK tests/test-string-input-visitor
LINK tests/test-string-output-visitor
LINK tests/test-qmp-event
LINK tests/test-opts-visitor
GTESTER tests/test-coroutine
LINK tests/test-visitor-serialization
GTESTER tests/test-iov
GTESTER tests/test-aio
GTESTER tests/test-aio-multithread
GTESTER tests/test-throttle
GTESTER tests/test-thread-pool
GTESTER tests/test-hbitmap
GTESTER tests/test-blockjob
GTESTER tests/test-blockjob-txn
GTESTER tests/test-x86-cpuid
GTESTER tests/test-xbzrle
GTESTER tests/test-vmstate
GTESTER tests/test-cutils
GTESTER tests/test-shift128
GTESTER tests/test-mul64
GTESTER tests/test-int128
GTESTER tests/rcutorture
GTESTER tests/test-rcu-list
GTESTER tests/test-qdist
GTESTER tests/test-qht
LINK tests/test-qht-par
GTESTER tests/test-bitops
GTESTER tests/test-bitcnt
GTESTER tests/test-qdev-global-props
GTESTER tests/check-qom-interface
GTESTER tests/check-qom-proplist
GTESTER tests/test-qemu-opts
GTESTER tests/test-write-threshold
GTESTER tests/test-crypto-hash
GTESTER tests/test-crypto-hmac
GTESTER tests/test-crypto-cipher
GTESTER tests/test-crypto-secret
GTESTER tests/test-crypto-tlscredsx509
GTESTER tests/test-crypto-tlssession
GTESTER tests/test-qga
GTESTER tests/test-timed-average
GTESTER tests/test-io-task
GTESTER tests/test-io-channel-socket
GTESTER tests/test-io-channel-file
GTESTER tests/test-io-channel-tls
GTESTER tests/test-io-channel-command
GTESTER tests/test-io-channel-buffer
GTESTER tests/test-base64
GTESTER tests/test-crypto-pbkdf
GTESTER tests/test-crypto-ivgen
GTESTER tests/test-crypto-afsplit
GTESTER tests/test-crypto-xts
GTESTER tests/test-crypto-block
GTESTER tests/test-logging
GTESTER tests/test-replication
GTESTER tests/test-bufferiszero
GTESTER tests/test-uuid
GTESTER tests/ptimer-test
GTESTER check-qtest-aarch64
GTESTER check-qtest-alpha
GTESTER check-qtest-arm
GTESTER check-qtest-cris
GTESTER check-qtest-i386
GTESTER check-qtest-lm32
GTESTER check-qtest-m68k
GTESTER check-qtest-microblazeel
GTESTER check-qtest-microblaze
GTESTER check-qtest-mips64el
GTESTER check-qtest-mips64
GTESTER check-qtest-mipsel
GTESTER check-qtest-mips
GTESTER check-qtest-moxie
GTESTER check-qtest-nios2
GTESTER check-qtest-or1k
GTESTER check-qtest-ppc64
GTESTER check-qtest-ppcemb
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
GTESTER check-qtest-ppc
GTESTER check-qtest-s390x
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
GTester: last random seed: R02S67b79687214a158c46bc466678067fdb
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
/var/tmp/patchew-tester-tmp-_t3ms3un/src/tests/Makefile.include:793: recipe for target 'check-qtest-s390x' failed
make: *** [check-qtest-s390x] Error 1
make: *** Waiting for unfinished jobs....
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
Warning! iasl couldn't parse the expected aml
"kvm" accelerator not found.
"kvm" accelerator not found.
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PULL 00/30] target-arm queue
2017-02-27 18:04 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2017-02-27 19:14 ` [Qemu-devel] [PULL 00/30] target-arm queue no-reply
@ 2017-02-28 12:07 ` Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2017-02-28 12:07 UTC (permalink / raw)
To: QEMU Developers
On 27 February 2017 at 18:04, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queu; includes all the NVIC rewrite patches.
> The QOMify-armv7m patchset hasn't got enough review just
> yet but I may be able to sneak it in before freeze
> tomorrow if it gets review. Didn't want to hold this lot
> up waiting, anyway.
>
> thanks
> -- PMM
>
>
> The following changes since commit 8f2d7c341184a95d05476ea3c45dbae2b9ddbe51:
>
> Merge remote-tracking branch 'remotes/berrange/tags/pull-qcrypto-2017-02-27-1' into staging (2017-02-27 15:33:21 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170227
>
> for you to fetch changes up to 94d5bcf5a7f3799660b62098a5183f161aad0601:
>
> hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-27 17:23:16 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * raspi2: implement RNG module, GPIO and new SD card controller
> (sufficient to boot new raspbian kernels)
> * sdhci: bugfixes for block transfers
> * virt: fix cpu object reference leak
> * Add missing fp_access_check() to aarch64 crypto instructions
> * cputlb: Don't assume do_unassigned_access() never returns
> * virt: Add a user option to disallow ITS instantiation
> * i.MX timers: fix reset handling
> * ARMv7M NVIC: rewrite to fix broken priority handling and masking
> * exynos: Fix proper mapping of CPUs by providing real cluster ID
> * exynos: Fix Linux kernel division by zero for PLLs
>
Unfortunately I see crashes or assert failures on the raspi2
model on OSX hosts. Not sure why OSX only, probably just that
the malloc/free has different patterns of reusing freed memory.
In any case we clearly didn't get the reparent-the-sdcard code
right, so I'm going to have to drop those patches for the moment :-(
thanks
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread