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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 01/21] armv7m: Abstract out the "load kernel" code
Date: Tue, 28 Feb 2017 17:15:56 +0000	[thread overview]
Message-ID: <1488302176-19463-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1488302176-19463-1-git-send-email-peter.maydell@linaro.org>

Abstract the "load kernel" code out of armv7m_init() into its own
function.  This includes the registration of the CPU reset function,
to parallel how we handle this for A profile cores.

We make the function public so that boards which choose to
directly instantiate an ARMv7M device object can call it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
---
 include/hw/arm/arm.h | 12 ++++++++++++
 hw/arm/armv7m.c      | 23 ++++++++++++++++++-----
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index c175c0e..a3f79d3 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -26,6 +26,18 @@ typedef enum {
 /* armv7m.c */
 DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
                       const char *kernel_filename, const char *cpu_model);
+/**
+ * armv7m_load_kernel:
+ * @cpu: CPU
+ * @kernel_filename: file to load
+ * @mem_size: mem_size: maximum image size to load
+ *
+ * Load the guest image for an ARMv7M system. This must be called by
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
+ * necessary to ensure that the CPU resets correctly on system reset,
+ * as well as for kernel loading.)
+ */
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
 
 /*
  * struct used as a parameter of the arm_load_kernel machine init
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 0c9ca7b..b2cc6e9 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -176,10 +176,6 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
     ARMCPU *cpu;
     CPUARMState *env;
     DeviceState *nvic;
-    int image_size;
-    uint64_t entry;
-    uint64_t lowaddr;
-    int big_endian;
 
     if (cpu_model == NULL) {
 	cpu_model = "cortex-m3";
@@ -199,6 +195,16 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
     qdev_init_nofail(nvic);
     sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
+    armv7m_load_kernel(cpu, kernel_filename, mem_size);
+    return nvic;
+}
+
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
+{
+    int image_size;
+    uint64_t entry;
+    uint64_t lowaddr;
+    int big_endian;
 
 #ifdef TARGET_WORDS_BIGENDIAN
     big_endian = 1;
@@ -224,8 +230,15 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
         }
     }
 
+    /* CPU objects (unlike devices) are not automatically reset on system
+     * reset, so we must always register a handler to do so. Unlike
+     * A-profile CPUs, we don't need to do anything special in the
+     * handler to arrange that it starts correctly.
+     * This is arguably the wrong place to do this, but it matches the
+     * way A-profile does it. Note that this means that every M profile
+     * board must call this function!
+     */
     qemu_register_reset(armv7m_reset, cpu);
-    return nvic;
 }
 
 static Property bitband_properties[] = {
-- 
2.7.4

  reply	other threads:[~2017-02-28 17:16 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-28 17:15 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2017-02-28 17:15 ` Peter Maydell [this message]
2017-02-28 17:15 ` [Qemu-devel] [PULL 02/21] armv7m: Move NVICState struct definition into header Peter Maydell
2017-02-28 17:15 ` [Qemu-devel] [PULL 03/21] armv7m: QOMify the armv7m container Peter Maydell
2017-02-28 17:15 ` [Qemu-devel] [PULL 04/21] armv7m: Use QOMified armv7m object in armv7m_init() Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 05/21] armv7m: Make ARMv7M object take memory region link Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 06/21] armv7m: Make NVIC expose a memory region rather than mapping itself Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 08/21] armv7m: Don't put core v7M devices under CONFIG_STELLARIS Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 09/21] armv7m: Split systick out from NVIC Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 10/21] stm32f205: Create armv7m object without using armv7m_init() Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 11/21] stm32f205: Rename 'nvic' local to 'armv7m' Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 12/21] update-linux-headers: update for 4.11 Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 13/21] update Linux headers to 4.11 Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 14/21] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 15/21] hw/intc/arm_gicv3_kvm: Implement get/put functions Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 16/21] target-arm: Add GICv3CPUState in CPUARMState struct Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 18/21] qdev: Have qdev_set_parent_bus() handle devices already on a bus Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 19/21] hw/sd: add card-reparenting function Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 20/21] bcm2835_gpio: add bcm2835 gpio controller Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 21/21] bcm2835: add sdhost and gpio controllers Peter Maydell
2017-03-01 19:28 ` [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell

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