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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 02/21] armv7m: Move NVICState struct definition into header
Date: Tue, 28 Feb 2017 17:15:57 +0000	[thread overview]
Message-ID: <1488302176-19463-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1488302176-19463-1-git-send-email-peter.maydell@linaro.org>

Move the NVICState struct definition into a header, so we can
embed it into other QOM objects like SoCs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
---
 include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
 hw/intc/armv7m_nvic.c        | 49 +-------------------------------
 2 files changed, 67 insertions(+), 48 deletions(-)
 create mode 100644 include/hw/arm/armv7m_nvic.h

diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
new file mode 100644
index 0000000..39b94ee
--- /dev/null
+++ b/include/hw/arm/armv7m_nvic.h
@@ -0,0 +1,66 @@
+/*
+ * ARMv7M NVIC object
+ *
+ * Copyright (c) 2017 Linaro Ltd
+ * Written by Peter Maydell <peter.maydell@linaro.org>
+ *
+ * This code is licensed under the GPL version 2 or later.
+ */
+
+#ifndef HW_ARM_ARMV7M_NVIC_H
+#define HW_ARM_ARMV7M_NVIC_H
+
+#include "target/arm/cpu.h"
+#include "hw/sysbus.h"
+
+#define TYPE_NVIC "armv7m_nvic"
+
+#define NVIC(obj) \
+    OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
+
+/* Highest permitted number of exceptions (architectural limit) */
+#define NVIC_MAX_VECTORS 512
+
+typedef struct VecInfo {
+    /* Exception priorities can range from -3 to 255; only the unmodifiable
+     * priority values for RESET, NMI and HardFault can be negative.
+     */
+    int16_t prio;
+    uint8_t enabled;
+    uint8_t pending;
+    uint8_t active;
+    uint8_t level; /* exceptions <=15 never set level */
+} VecInfo;
+
+typedef struct NVICState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    ARMCPU *cpu;
+
+    VecInfo vectors[NVIC_MAX_VECTORS];
+    uint32_t prigroup;
+
+    /* vectpending and exception_prio are both cached state that can
+     * be recalculated from the vectors[] array and the prigroup field.
+     */
+    unsigned int vectpending; /* highest prio pending enabled exception */
+    int exception_prio; /* group prio of the highest prio active exception */
+
+    struct {
+        uint32_t control;
+        uint32_t reload;
+        int64_t tick;
+        QEMUTimer *timer;
+    } systick;
+
+    MemoryRegion sysregmem;
+    MemoryRegion container;
+
+    uint32_t num_irq;
+    qemu_irq excpout;
+    qemu_irq sysresetreq;
+} NVICState;
+
+#endif
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 76097b4..f2ada39 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -17,6 +17,7 @@
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "hw/arm/arm.h"
+#include "hw/arm/armv7m_nvic.h"
 #include "target/arm/cpu.h"
 #include "exec/address-spaces.h"
 #include "qemu/log.h"
@@ -47,7 +48,6 @@
  * "exception" more or less interchangeably.
  */
 #define NVIC_FIRST_IRQ 16
-#define NVIC_MAX_VECTORS 512
 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
 
 /* Effective running priority of the CPU when no exception is active
@@ -55,53 +55,6 @@
  */
 #define NVIC_NOEXC_PRIO 0x100
 
-typedef struct VecInfo {
-    /* Exception priorities can range from -3 to 255; only the unmodifiable
-     * priority values for RESET, NMI and HardFault can be negative.
-     */
-    int16_t prio;
-    uint8_t enabled;
-    uint8_t pending;
-    uint8_t active;
-    uint8_t level; /* exceptions <=15 never set level */
-} VecInfo;
-
-typedef struct NVICState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-    /*< public >*/
-
-    ARMCPU *cpu;
-
-    VecInfo vectors[NVIC_MAX_VECTORS];
-    uint32_t prigroup;
-
-    /* vectpending and exception_prio are both cached state that can
-     * be recalculated from the vectors[] array and the prigroup field.
-     */
-    unsigned int vectpending; /* highest prio pending enabled exception */
-    int exception_prio; /* group prio of the highest prio active exception */
-
-    struct {
-        uint32_t control;
-        uint32_t reload;
-        int64_t tick;
-        QEMUTimer *timer;
-    } systick;
-
-    MemoryRegion sysregmem;
-    MemoryRegion container;
-
-    uint32_t num_irq;
-    qemu_irq excpout;
-    qemu_irq sysresetreq;
-} NVICState;
-
-#define TYPE_NVIC "armv7m_nvic"
-
-#define NVIC(obj) \
-    OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
-
 static const uint8_t nvic_id[] = {
     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
 };
-- 
2.7.4

  parent reply	other threads:[~2017-02-28 17:16 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-28 17:15 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2017-02-28 17:15 ` [Qemu-devel] [PULL 01/21] armv7m: Abstract out the "load kernel" code Peter Maydell
2017-02-28 17:15 ` Peter Maydell [this message]
2017-02-28 17:15 ` [Qemu-devel] [PULL 03/21] armv7m: QOMify the armv7m container Peter Maydell
2017-02-28 17:15 ` [Qemu-devel] [PULL 04/21] armv7m: Use QOMified armv7m object in armv7m_init() Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 05/21] armv7m: Make ARMv7M object take memory region link Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 06/21] armv7m: Make NVIC expose a memory region rather than mapping itself Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 08/21] armv7m: Don't put core v7M devices under CONFIG_STELLARIS Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 09/21] armv7m: Split systick out from NVIC Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 10/21] stm32f205: Create armv7m object without using armv7m_init() Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 11/21] stm32f205: Rename 'nvic' local to 'armv7m' Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 12/21] update-linux-headers: update for 4.11 Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 13/21] update Linux headers to 4.11 Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 14/21] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 15/21] hw/intc/arm_gicv3_kvm: Implement get/put functions Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 16/21] target-arm: Add GICv3CPUState in CPUARMState struct Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 18/21] qdev: Have qdev_set_parent_bus() handle devices already on a bus Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 19/21] hw/sd: add card-reparenting function Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 20/21] bcm2835_gpio: add bcm2835 gpio controller Peter Maydell
2017-02-28 17:16 ` [Qemu-devel] [PULL 21/21] bcm2835: add sdhost and gpio controllers Peter Maydell
2017-03-01 19:28 ` [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell

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