[Qemu-devel] [PATCH v1 0/3] target/ppc: floating point multiply-add fixes

[Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>]

Exception handling in fmadd/fmsub/fnmadd/fnmsub isnt correct as the 
order of checking could give wrong settings in FPSCR.

For example, (x * y) + z, if x = infinity, y = zero and z = snan. 
After the execution of instruction VXNAN and VXIMZ both should be set. For 
this correct the ordering in the float64_maddsub_update_excp() as follows:

      * If x, y or z is an SNaN, vxsnan_flag is set to 1.
      * If x is a Zero and y, is an Infinity or x is an Infinity and y is
        an Zero, vximz_flag is set to 1.
      * If the product of x and y is an Infinity and z is an Infinity of
        the opposite sign, vxisi_flag is set to 1.

Moreover, all vector multiply-add/substract and vector scalar multiply-add/sub 
had the bug. VXISI should be set only when (∞ - ∞), where as the instruction was
doing it wrong, was just checking ((a == ∞ OR b == ∞) && (c == ∞)). There are two 
issues here:

1. infinity can be +ve or -ve, i.e.  (∞ + (-∞)), should result in setting VXISI
2. Need to take care of the operation (add or sub). (∞ + ∞) should not set VXISI

Patch:
01: Fixes the order of checking and makes them independent as per 
    the ISA

02: Introduces the macro to be used by Vector Scalar and Vector Multiply-Add

03: Make Vector Scalar and Vector Multiply Add use the macro for updating 
    exception flags 

Changelog:
v0:
* Use ALL CAPS for macro arguments
* Correct the argument type in the function

Nikunj A Dadhania (3):
  target/ppc: fmadd check for excp independently
  target/ppc: fmadd: add macro for updating flags
  target/ppc: use helper for excp handling

 target/ppc/fpu_helper.c | 77 ++++++++++++++++++++-----------------------------
 1 file changed, 32 insertions(+), 45 deletions(-)

-- 
2.7.4