From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 2/4] arm: Don't decode MRS(banked) or MSR(banked) for M profile
Date: Mon, 20 Mar 2017 12:54:34 +0000 [thread overview]
Message-ID: <1490014476-25672-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1490014476-25672-1-git-send-email-peter.maydell@linaro.org>
M profile doesn't have the MSR(banked) and MRS(banked) instructions
and uses the encodings for different kinds of M-profile MRS/MSR.
Guard the relevant bits of the decode logic to make sure we don't
accidentally fall into them by accident on M-profile.
(The bit being checked for this (bit 5) is part of the SYSm field on
M-profile, but since no currently allocated system registers have
encodings with bit 5 of SYSm set, this hasn't been a problem in
practice.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org
---
target/arm/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 216852b..a5f5a28 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10500,7 +10500,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_exception_return(s, tmp);
break;
case 6: /* MRS */
- if (extract32(insn, 5, 1)) {
+ if (extract32(insn, 5, 1) &&
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
/* MRS (banked) */
int sysm = extract32(insn, 16, 4) |
(extract32(insn, 4, 1) << 4);
@@ -10521,7 +10522,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
store_reg(s, rd, tmp);
break;
case 7: /* MRS */
- if (extract32(insn, 5, 1)) {
+ if (extract32(insn, 5, 1) &&
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
/* MRS (banked) */
int sysm = extract32(insn, 16, 4) |
(extract32(insn, 4, 1) << 4);
--
2.7.4
next prev parent reply other threads:[~2017-03-20 12:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-20 12:54 [Qemu-devel] [PULL for-2.9 0/4] target-arm queue Peter Maydell
2017-03-20 12:54 ` [Qemu-devel] [PULL 1/4] arm: HVC and SMC encodings don't exist for M profile Peter Maydell
2017-03-20 12:54 ` Peter Maydell [this message]
2017-03-20 12:54 ` [Qemu-devel] [PULL 3/4] arm: Enforce should-be-1 bits in MRS decoding Peter Maydell
2017-03-20 12:54 ` [Qemu-devel] [PULL 4/4] arm: Fix APSR writes via M profile MSR Peter Maydell
2017-03-20 13:52 ` [Qemu-devel] [PULL for-2.9 0/4] target-arm queue Peter Maydell
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