From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH v3 0/8] ppc/pnv: interrupt controller (POWER8)
Date: Tue, 28 Mar 2017 09:32:24 +0200 [thread overview]
Message-ID: <1490686352-24017-1-git-send-email-clg@kaod.org> (raw)
Hello,
Here is a series adding support for the interrupt controller as found
on a POWER8 system. POWER9 uses a different interrupt controller
called XIVE, still to be worked on.
The initial patches are more cleanups of the XICS layer which move the
IRQ 'server' number mapping under the machine handlers. The PowerNV
machine is then extended with the Interrupt Source Control (ICS), the
Interrupt Control Presenter (ICP) objects and the Interrupt Management
area.
To test, grab a kernel and a rootfs image here :
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz
The full patchset is available here :
https://github.com/legoater/qemu/commits/powernv-ipmi-2.9
Thanks,
C.
Changes since v2:
- removed the ICS list from the PowerNV machine
- changed the 'icp' backlink type to be an 'Object'
Changes since v1:
- introduced PnvICPState to hold the ICP memory region
- handled pir-to-cpu_index mapping under the machine icp_get handler
- added multichip support
- removed ics_eoi handler (came from a bug in PHB3_MSI)
- kept PSI and OCC model for later, when this part is done.
Cédric Le Goater (8):
ppc/xics: introduce an 'icp' backlink under PowerPCCPU
spapr: move the IRQ server number mapping under the machine
ppc/xics: add a realize() handler to ICPStateClass
ppc/pnv: add a PnvICPState object
ppc/pnv: create the ICP and ICS objects under the machine
ppc/pnv: add a helper to calculate MMIO addresses registers
ppc/pnv: link the CPUs to the machine XICSFabric
ppc/pnv: add memory regions for the ICP registers
hw/intc/Makefile.objs | 1 +
hw/intc/xics.c | 9 ++-
hw/intc/xics_pnv.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/intc/xics_spapr.c | 25 ++-----
hw/ppc/pnv.c | 179 +++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_core.c | 20 ++++--
hw/ppc/spapr.c | 3 +-
hw/ppc/spapr_cpu_core.c | 5 +-
include/hw/ppc/pnv.h | 34 ++++++++-
include/hw/ppc/xics.h | 13 ++++
target/ppc/cpu.h | 1 +
11 files changed, 443 insertions(+), 27 deletions(-)
create mode 100644 hw/intc/xics_pnv.c
--
2.7.4
next reply other threads:[~2017-03-28 7:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-28 7:32 Cédric Le Goater [this message]
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 1/8] ppc/xics: introduce an 'icp' backlink under PowerPCCPU Cédric Le Goater
2017-03-29 4:11 ` David Gibson
2017-03-29 7:14 ` Cédric Le Goater
2017-03-30 1:26 ` David Gibson
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 2/8] spapr: move the IRQ server number mapping under the machine Cédric Le Goater
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 3/8] ppc/xics: add a realize() handler to ICPStateClass Cédric Le Goater
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 4/8] ppc/pnv: add a PnvICPState object Cédric Le Goater
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 5/8] ppc/pnv: create the ICP and ICS objects under the machine Cédric Le Goater
2017-03-29 5:18 ` David Gibson
2017-03-29 8:13 ` Cédric Le Goater
2017-03-30 1:55 ` David Gibson
2017-03-30 8:15 ` Cédric Le Goater
2017-04-02 6:11 ` David Gibson
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 6/8] ppc/pnv: add a helper to calculate MMIO addresses registers Cédric Le Goater
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 7/8] ppc/pnv: link the CPUs to the machine XICSFabric Cédric Le Goater
2017-03-29 5:20 ` David Gibson
2017-03-29 7:16 ` Cédric Le Goater
2017-03-28 7:32 ` [Qemu-devel] [PATCH v3 8/8] ppc/pnv: add memory regions for the ICP registers Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1490686352-24017-1-git-send-email-clg@kaod.org \
--to=clg@kaod.org \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).