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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Jason Wang" <jasowang@redhat.com>,
	"Dmitry Fleytman" <dmitry@daynix.com>,
	"Samuel Thibault" <samuel.thibault@ens-lyon.org>,
	"Jan Kiszka" <jan.kiszka@siemens.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 2/4] net/ftgmac100: add a 'aspeed' property
Date: Sat,  1 Apr 2017 14:57:55 +0200	[thread overview]
Message-ID: <1491051477-10455-3-git-send-email-clg@kaod.org> (raw)
In-Reply-To: <1491051477-10455-1-git-send-email-clg@kaod.org>

The Aspeed SoCs have a different definition of the end of the ring
buffer bit. Add a property to specify which set of bits should be used
by the NIC.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/net/ftgmac100.c         | 19 ++++++++++++++++---
 include/hw/net/ftgmac100.h |  4 ++++
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 331e87391962..8867c435ba9d 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -133,6 +133,7 @@ struct ftgmac100_txdes {
 #define FTGMAC100_TXDES0_CRC_ERR         (1 << 19)
 #define FTGMAC100_TXDES0_LTS             (1 << 28)
 #define FTGMAC100_TXDES0_FTS             (1 << 29)
+#define FTGMAC100_TXDES0_EDOTR_ASPEED    (1 << 30)
 #define FTGMAC100_TXDES0_TXDMA_OWN       (1 << 31)
 
 #define FTGMAC100_TXDES1_VLANTAG_CI(x)   ((x) & 0xffff)
@@ -168,6 +169,7 @@ struct ftgmac100_rxdes {
 #define FTGMAC100_RXDES0_PAUSE_FRAME     (1 << 25)
 #define FTGMAC100_RXDES0_LRS             (1 << 28)
 #define FTGMAC100_RXDES0_FRS             (1 << 29)
+#define FTGMAC100_RXDES0_EDORR_ASPEED    (1 << 30)
 #define FTGMAC100_RXDES0_RXPKT_RDY       (1 << 31)
 
 #define FTGMAC100_RXDES1_VLANTAG_CI      0xffff
@@ -387,7 +389,7 @@ static uint32_t ftgmac100_find_txdes(Ftgmac100State *s, uint32_t addr)
 
     while (1) {
         ftgmac100_read_bd(&bd, addr);
-        if (bd.des0 & (FTGMAC100_TXDES0_FTS | FTGMAC100_TXDES0_EDOTR)) {
+        if (bd.des0 & (FTGMAC100_TXDES0_FTS | s->txdes0_edotr)) {
             break;
         }
         addr += sizeof(Ftgmac100Desc);
@@ -453,7 +455,7 @@ static void ftgmac100_do_tx(Ftgmac100State *s, uint32_t tx_ring,
         /* Write back the modified descriptor.  */
         ftgmac100_write_bd(&bd, addr);
         /* Advance to the next descriptor.  */
-        if (bd.des0 & FTGMAC100_TXDES0_EDOTR) {
+        if (bd.des0 & s->txdes0_edotr) {
             addr = tx_ring;
         } else {
             addr += sizeof(Ftgmac100Desc);
@@ -856,7 +858,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
             s->isr |= FTGMAC100_INT_RPKT_FIFO;
         }
         ftgmac100_write_bd(&bd, addr);
-        if (bd.des0 & FTGMAC100_RXDES0_EDORR) {
+        if (bd.des0 & s->rxdes0_edorr) {
             addr = s->rx_ring;
         } else {
             addr += sizeof(Ftgmac100Desc);
@@ -897,6 +899,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
     Ftgmac100State *s = FTGMAC100(dev);
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
+    if (s->aspeed) {
+        s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
+        s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
+    } else {
+        s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
+        s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
+    }
+
     memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
                           TYPE_FTGMAC100, 0x2000);
     sysbus_init_mmio(sbd, &s->iomem);
@@ -941,11 +951,14 @@ static const VMStateDescription vmstate_ftgmac100 = {
         VMSTATE_UINT32(phy_advertise, Ftgmac100State),
         VMSTATE_UINT32(phy_int, Ftgmac100State),
         VMSTATE_UINT32(phy_int_mask, Ftgmac100State),
+        VMSTATE_UINT32(txdes0_edotr, Ftgmac100State),
+        VMSTATE_UINT32(rxdes0_edorr, Ftgmac100State),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static Property ftgmac100_properties[] = {
+    DEFINE_PROP_BOOL("aspeed", Ftgmac100State, aspeed, false),
     DEFINE_NIC_PROPERTIES(Ftgmac100State, conf),
     DEFINE_PROP_END_OF_LIST(),
 };
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
index 3bb4fe1a3ece..feb387bf0e2d 100644
--- a/include/hw/net/ftgmac100.h
+++ b/include/hw/net/ftgmac100.h
@@ -53,6 +53,10 @@ typedef struct Ftgmac100State {
     uint32_t phy_advertise;
     uint32_t phy_int;
     uint32_t phy_int_mask;
+
+    bool aspeed;
+    uint32_t txdes0_edotr;
+    uint32_t rxdes0_edorr;
 } Ftgmac100State;
 
 #endif
-- 
2.7.4

  parent reply	other threads:[~2017-04-01 12:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-01 12:57 [Qemu-devel] [PATCH 0/4] FTGMAC100 nic model for the Aspeed SoCs Cédric Le Goater
2017-04-01 12:57 ` [Qemu-devel] [PATCH 1/4] net: add FTGMAC100 support Cédric Le Goater
2017-04-10 13:43   ` Peter Maydell
2017-04-12 17:29     ` Cédric Le Goater
2017-04-12 17:37       ` Peter Maydell
2017-04-01 12:57 ` Cédric Le Goater [this message]
2017-04-01 12:57 ` [Qemu-devel] [PATCH 3/4] aspeed: add a FTGMAC100 nic Cédric Le Goater
2017-04-01 12:57 ` [Qemu-devel] [PATCH 4/4] slirp: add a fake NC-SI backend Cédric Le Goater

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