From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, "Richard Henderson" <rth@twiddle.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PATCH v2 3/9] arm: Factor out "generate right kind of step exception"
Date: Mon, 10 Apr 2017 18:13:33 +0100 [thread overview]
Message-ID: <1491844419-12485-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1491844419-12485-1-git-send-email-peter.maydell@linaro.org>
We currently have two places that do:
if (dc->ss_active) {
gen_step_complete_exception(dc);
} else {
gen_exception_internal(EXCP_DEBUG);
}
Factor this out into its own function, as we're about to add
a third place that needs the same logic.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ddc62b6..870e320 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -296,6 +296,19 @@ static void gen_step_complete_exception(DisasContext *s)
s->is_jmp = DISAS_EXC;
}
+static void gen_singlestep_exception(DisasContext *s)
+{
+ /* Generate the right kind of exception for singlestep, which is
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
+ * gdb singlestepping.
+ */
+ if (s->ss_active) {
+ gen_step_complete_exception(s);
+ } else {
+ gen_exception_internal(EXCP_DEBUG);
+ }
+}
+
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -11998,24 +12011,15 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
gen_set_pc_im(dc, dc->pc);
/* fall through */
default:
- if (dc->ss_active) {
- gen_step_complete_exception(dc);
- } else {
- /* FIXME: Single stepping a WFI insn will not halt
- the CPU. */
- gen_exception_internal(EXCP_DEBUG);
- }
+ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
+ gen_singlestep_exception(dc);
}
if (dc->condjmp) {
/* "Condition failed" instruction codepath. */
gen_set_label(dc->condlabel);
gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc);
- if (dc->ss_active) {
- gen_step_complete_exception(dc);
- } else {
- gen_exception_internal(EXCP_DEBUG);
- }
+ gen_singlestep_exception(dc);
}
} else {
/* While branches must always occur at the end of an IT block,
--
2.7.4
next prev parent reply other threads:[~2017-04-10 17:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-10 17:13 [Qemu-devel] [PATCH v2 0/9] arm: Implement M profile exception return properly Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 1/9] arm: Don't implement BXJ on M-profile CPUs Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 2/9] arm: Thumb shift operations should not permit interworking branches Peter Maydell
2017-04-10 17:13 ` Peter Maydell [this message]
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 4/9] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 5/9] arm: Move condition-failed codepath generation out of if() Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 6/9] arm: Abstract out "are we singlestepping" test to utility function Peter Maydell
2017-04-10 18:54 ` Philippe Mathieu-Daudé
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 7/9] arm: Track M profile handler mode state in TB flags Peter Maydell
2017-04-17 4:20 ` Philippe Mathieu-Daudé
2017-04-20 14:25 ` Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 8/9] arm: Implement M profile exception return properly Peter Maydell
2017-04-10 17:13 ` [Qemu-devel] [PATCH v2 9/9] arm: Remove workarounds for old M-profile exception return implementation Peter Maydell
2017-04-15 12:31 ` [Qemu-devel] [PATCH v2 0/9] arm: Implement M profile exception return properly Richard Henderson
2017-04-20 14:28 ` Peter Maydell
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