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Message-ID: <14921864.post@talk.nabble.com>
Date: Thu, 17 Jan 2008 07:34:45 -0800 (PST)
From: TeLeMan <geleman@gmail.com>
Subject: [Qemu-devel] [PATCH]SVM CR8 undefined bug fix
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To: qemu-devel@nongnu.org


env->cr[8] used by SVM codes was not defined.

http://www.nabble.com/file/p14921864/svm_cr8.patch svm_cr8.patch: 

diff -p -u qemu.orig/target-i386/cpu.h qemu/target-i386/cpu.h
--- qemu.orig/target-i386/cpu.h	Mon Jan 14 11:11:08 2008
+++ qemu/target-i386/cpu.h	Thu Jan 17 23:21:22 2008
@@ -493,7 +493,7 @@ typedef struct CPUX86State {
     SegmentCache gdt; /* only base and limit are used */
     SegmentCache idt; /* only base and limit are used */
 
-    target_ulong cr[5]; /* NOTE: cr1 is unused */
+    target_ulong cr[9]; /* NOTE: cr1,cr5-cr7 are unused */
     uint32_t a20_mask;
 
     /* FPU state */
diff -p -u qemu.orig/target-i386/helper.c qemu/target-i386/helper.c
--- qemu.orig/target-i386/helper.c	Mon Jan 14 11:11:08 2008
+++ qemu/target-i386/helper.c	Thu Jan 17 23:24:04 2008
@@ -2718,6 +2718,7 @@ void helper_movl_crN_T0(int reg)
         break;
     case 8:
         cpu_set_apic_tpr(env, T0);
+        env->cr[8] = T0;
         break;
     default:
         env->cr[reg] = T0;
@@ -4065,6 +4066,7 @@ void helper_vmrun(target_ulong addr)
     int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
control.int_ctl));
     if (int_ctl & V_INTR_MASKING_MASK) {
         env->cr[8] = int_ctl & V_TPR_MASK;
+	cpu_set_apic_tpr(env,env->cr[8]);
         if (env->eflags & IF_MASK)
             env->hflags |= HF_HIF_MASK;
     }
@@ -4376,8 +4378,10 @@ void vmexit(uint64_t exit_code, uint64_t
     cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.cr0)) | CR0_PE_MASK);
     cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.cr4)));
     cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.cr3)));
-    if (int_ctl & V_INTR_MASKING_MASK)
+    if (int_ctl & V_INTR_MASKING_MASK) {
         env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.cr8));
+        cpu_set_apic_tpr(env,env->cr[8]);
+    }
     /* we need to set the efer after the crs so the hidden flags get set
properly */
 #ifdef TARGET_X86_64
     env->efer  = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
save.efer));

-- 
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