From: "Emilio G. Cota" <cota@braap.org>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Richard Henderson <rth@twiddle.net>,
Peter Maydell <peter.maydell@linaro.org>,
Eduardo Habkost <ehabkost@redhat.com>,
Andrzej Zaborowski <balrogg@gmail.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Alexander Graf <agraf@suse.de>, Stefan Weil <sw@weilnetz.de>,
qemu-arm@nongnu.org, alex.bennee@linaro.org,
Pranith Kumar <bobby.prani+qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v3 07/10] target/i386: introduce gen_jr helper to generate lookup_and_goto_ptr
Date: Wed, 26 Apr 2017 02:23:20 -0400 [thread overview]
Message-ID: <1493187803-4510-8-git-send-email-cota@braap.org> (raw)
In-Reply-To: <1493187803-4510-1-git-send-email-cota@braap.org>
This helper will be used by subsequent changes.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/i386/translate.c | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 1d1372f..59f6eaa 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -141,6 +141,7 @@ typedef struct DisasContext {
} DisasContext;
static void gen_eob(DisasContext *s);
+static void gen_jr(DisasContext *s, TCGv dest);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);
@@ -2509,7 +2510,8 @@ static void gen_bnd_jmp(DisasContext *s)
If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set.
If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of
S->TF. This is used by the syscall/sysret insns. */
-static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf)
+static void
+gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr)
{
gen_update_cc_op(s);
@@ -2530,6 +2532,13 @@ static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf)
tcg_gen_exit_tb(0);
} else if (s->tf) {
gen_helper_single_step(cpu_env);
+ } else if (jr) {
+ TCGv vaddr = tcg_temp_new();
+
+ tcg_gen_ld_tl(vaddr, cpu_env, offsetof(CPUX86State, segs[R_CS].base));
+ tcg_gen_add_tl(vaddr, vaddr, jr);
+ tcg_gen_lookup_and_goto_ptr(vaddr);
+ tcg_temp_free(vaddr);
} else {
tcg_gen_exit_tb(0);
}
@@ -2540,13 +2549,19 @@ static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf)
If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set. */
static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit)
{
- gen_eob_worker(s, inhibit, false);
+ gen_eob_worker(s, inhibit, false, NULL);
}
/* End of block, resetting the inhibit irq flag. */
static void gen_eob(DisasContext *s)
{
- gen_eob_worker(s, false, false);
+ gen_eob_worker(s, false, false, NULL);
+}
+
+/* Jump to register */
+static void gen_jr(DisasContext *s, TCGv dest)
+{
+ gen_eob_worker(s, false, false, dest);
}
/* generate a jump to eip. No segment change must happen before as a
@@ -7131,7 +7146,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* TF handling for the syscall insn is different. The TF bit is checked
after the syscall insn completes. This allows #DB to not be
generated after one has entered CPL0 if TF is set in FMASK. */
- gen_eob_worker(s, false, true);
+ gen_eob_worker(s, false, true, NULL);
break;
case 0x107: /* sysret */
if (!s->pe) {
@@ -7146,7 +7161,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
checked after the sysret insn completes. This allows #DB to be
generated "as if" the syscall insn in userspace has just
completed. */
- gen_eob_worker(s, false, true);
+ gen_eob_worker(s, false, true, NULL);
}
break;
#endif
--
2.7.4
next prev parent reply other threads:[~2017-04-26 6:23 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-26 6:23 [Qemu-devel] [PATCH v3 00/10] TCG optimizations for 2.10 Emilio G. Cota
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 01/10] tcg-runtime: add lookup_tb_ptr helper Emilio G. Cota
2017-04-26 7:50 ` Paolo Bonzini
2017-04-26 8:40 ` Richard Henderson
2017-04-26 21:56 ` Emilio G. Cota
2017-04-26 22:29 ` Richard Henderson
2017-04-26 22:45 ` Emilio G. Cota
2017-04-26 23:11 ` Emilio G. Cota
2017-04-26 23:25 ` Emilio G. Cota
2017-04-26 23:17 ` Emilio G. Cota
2017-04-26 10:29 ` Alex Bennée
2017-04-26 10:43 ` Richard Henderson
2017-04-26 15:11 ` Paolo Bonzini
2017-04-26 16:16 ` Alex Bennée
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 02/10] tcg: introduce goto_ptr opcode Emilio G. Cota
2017-04-26 8:30 ` Richard Henderson
2017-04-26 12:12 ` Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 03/10] tcg: export tcg_gen_lookup_and_goto_ptr Emilio G. Cota
2017-04-26 8:29 ` Richard Henderson
2017-04-26 10:33 ` Alex Bennée
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 04/10] tcg/i386: implement goto_ptr op Emilio G. Cota
2017-04-26 8:28 ` Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 05/10] target/arm: optimize cross-page direct jumps in softmmu Emilio G. Cota
2017-04-26 8:27 ` Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 06/10] target/arm: optimize indirect branches Emilio G. Cota
2017-04-26 7:54 ` Richard Henderson
2017-04-27 3:20 ` Emilio G. Cota
2017-04-27 10:25 ` Aurelien Jarno
2017-04-26 6:23 ` Emilio G. Cota [this message]
2017-04-26 8:26 ` [Qemu-devel] [PATCH v3 07/10] target/i386: introduce gen_jr helper to generate lookup_and_goto_ptr Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 08/10] target/i386: optimize cross-page direct jumps in softmmu Emilio G. Cota
2017-04-26 8:25 ` Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 09/10] target/i386: optimize indirect branches Emilio G. Cota
2017-04-26 8:24 ` Richard Henderson
2017-04-26 6:23 ` [Qemu-devel] [PATCH v3 10/10] tb-hash: improve tb_jmp_cache hash function in user mode Emilio G. Cota
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