* [Qemu-devel] [PATCH 1/6] aspeed/i2c: improve command handling
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 2/6] aspeed/i2c: handle LAST command under the RX command Cédric Le Goater
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
Multiple I2C commands can be fired simultaneously and the controller
execute the commands following these priorities:
(1) Master Start Command
(2) Master Transmit Command
(3) Slave Transmit Command or Master Receive Command
(4) Master Stop Command
The current code is incorrect with respect to the above sequence and
needs to be reworked to handle each individual command.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/i2c/aspeed_i2c.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index ce5b1f0fa493..56a4fdf5c542 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -171,6 +171,7 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
{
+ bus->cmd &= ~0xFFFF;
bus->cmd |= value & 0xFFFF;
bus->intr_status = 0;
@@ -182,15 +183,27 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
bus->intr_status |= I2CD_INTR_TX_ACK;
}
- } else if (bus->cmd & I2CD_M_TX_CMD) {
+ /* START command is also a TX command, as the slave address is
+ * sent on the bus */
+ bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
+
+ /* No slave found */
+ if (!i2c_bus_busy(bus->bus)) {
+ return;
+ }
+ }
+
+ if (bus->cmd & I2CD_M_TX_CMD) {
if (i2c_send(bus->bus, bus->buf)) {
bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
i2c_end_transfer(bus->bus);
} else {
bus->intr_status |= I2CD_INTR_TX_ACK;
}
+ bus->cmd &= ~I2CD_M_TX_CMD;
+ }
- } else if (bus->cmd & I2CD_M_RX_CMD) {
+ if (bus->cmd & I2CD_M_RX_CMD) {
int ret = i2c_recv(bus->bus);
if (ret < 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -199,6 +212,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
bus->intr_status |= I2CD_INTR_RX_DONE;
}
bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
+ bus->cmd &= ~I2CD_M_RX_CMD;
}
if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
@@ -208,11 +222,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
i2c_end_transfer(bus->bus);
bus->intr_status |= I2CD_INTR_NORMAL_STOP;
}
+ bus->cmd &= ~I2CD_M_STOP_CMD;
}
-
- /* command is handled, reset it and check for interrupts */
- bus->cmd &= ~0xFFFF;
- aspeed_i2c_bus_raise_interrupt(bus);
}
static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
@@ -262,6 +273,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
}
aspeed_i2c_bus_handle_cmd(bus, value);
+ aspeed_i2c_bus_raise_interrupt(bus);
break;
default:
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 2/6] aspeed/i2c: handle LAST command under the RX command
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 1/6] aspeed/i2c: improve command handling Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 3/6] aspeed/i2c: introduce a state machine Cédric Le Goater
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
Today, the LAST command is handled with the STOP command but this is
incorrect. Also nack the I2C bus when a LAST is issued.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/i2c/aspeed_i2c.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 56a4fdf5c542..67004c675359 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -203,7 +203,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
bus->cmd &= ~I2CD_M_TX_CMD;
}
- if (bus->cmd & I2CD_M_RX_CMD) {
+ if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
int ret = i2c_recv(bus->bus);
if (ret < 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -212,10 +212,13 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
bus->intr_status |= I2CD_INTR_RX_DONE;
}
bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
- bus->cmd &= ~I2CD_M_RX_CMD;
+ if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
+ i2c_nack(bus->bus);
+ }
+ bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
}
- if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
+ if (bus->cmd & I2CD_M_STOP_CMD) {
if (!i2c_bus_busy(bus->bus)) {
bus->intr_status |= I2CD_INTR_ABNORMAL;
} else {
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 3/6] aspeed/i2c: introduce a state machine
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 1/6] aspeed/i2c: improve command handling Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 2/6] aspeed/i2c: handle LAST command under the RX command Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 4/6] aspeed: add some I2C devices to the Aspeed machines Cédric Le Goater
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
The Aspeed I2C controller maintains a state machine in the command
register, which is mostly used for debug.
Let's start adding a few states to handle abnormal STOP
commands. Today, the model uses the busy status of the bus as a
condition to do so but it is not precise enough.
Also remove the ABNORMAL bit for failing TX commands. This is
incorrect with respect to the specs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/i2c/aspeed_i2c.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 67004c675359..c762c7366ad9 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -169,6 +169,21 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
}
}
+static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
+{
+ bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
+ bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
+}
+
+static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
+{
+ return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
+}
+
+/*
+ * The state machine needs some refinement. It is only used to track
+ * invalid STOP commands for the moment.
+ */
static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
{
bus->cmd &= ~0xFFFF;
@@ -176,6 +191,11 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
bus->intr_status = 0;
if (bus->cmd & I2CD_M_START_CMD) {
+ uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
+ I2CD_MSTARTR : I2CD_MSTART;
+
+ aspeed_i2c_set_state(bus, state);
+
if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
extract32(bus->buf, 0, 1))) {
bus->intr_status |= I2CD_INTR_TX_NAK;
@@ -191,20 +211,26 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
if (!i2c_bus_busy(bus->bus)) {
return;
}
+ aspeed_i2c_set_state(bus, I2CD_MACTIVE);
}
if (bus->cmd & I2CD_M_TX_CMD) {
+ aspeed_i2c_set_state(bus, I2CD_MTXD);
if (i2c_send(bus->bus, bus->buf)) {
- bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
+ bus->intr_status |= (I2CD_INTR_TX_NAK);
i2c_end_transfer(bus->bus);
} else {
bus->intr_status |= I2CD_INTR_TX_ACK;
}
bus->cmd &= ~I2CD_M_TX_CMD;
+ aspeed_i2c_set_state(bus, I2CD_MACTIVE);
}
if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
- int ret = i2c_recv(bus->bus);
+ int ret;
+
+ aspeed_i2c_set_state(bus, I2CD_MRXD);
+ ret = i2c_recv(bus->bus);
if (ret < 0) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
ret = 0xff;
@@ -216,16 +242,20 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
i2c_nack(bus->bus);
}
bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
+ aspeed_i2c_set_state(bus, I2CD_MACTIVE);
}
if (bus->cmd & I2CD_M_STOP_CMD) {
- if (!i2c_bus_busy(bus->bus)) {
+ if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
bus->intr_status |= I2CD_INTR_ABNORMAL;
} else {
+ aspeed_i2c_set_state(bus, I2CD_MSTOP);
i2c_end_transfer(bus->bus);
bus->intr_status |= I2CD_INTR_NORMAL_STOP;
}
bus->cmd &= ~I2CD_M_STOP_CMD;
+ aspeed_i2c_set_state(bus, I2CD_IDLE);
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 4/6] aspeed: add some I2C devices to the Aspeed machines
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
` (2 preceding siblings ...)
2017-05-15 5:51 ` [Qemu-devel] [PATCH 3/6] aspeed/i2c: introduce a state machine Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-05-15 5:51 ` [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1,2,3} device model Cédric Le Goater
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to
the AST2500 EVB to start with.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 283c03881493..e824ea87a9af 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -39,6 +39,7 @@ typedef struct AspeedBoardConfig {
const char *fmc_model;
const char *spi_model;
uint32_t num_cs;
+ void (*i2c_init)(AspeedBoardState *bmc);
} AspeedBoardConfig;
enum {
@@ -82,6 +83,9 @@ enum {
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
+static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
+
static const AspeedBoardConfig aspeed_boards[] = {
[PALMETTO_BMC] = {
.soc_name = "ast2400-a1",
@@ -89,6 +93,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
.fmc_model = "n25q256a",
.spi_model = "mx25l25635e",
.num_cs = 1,
+ .i2c_init = palmetto_bmc_i2c_init,
},
[AST2500_EVB] = {
.soc_name = "ast2500-a1",
@@ -96,6 +101,7 @@ static const AspeedBoardConfig aspeed_boards[] = {
.fmc_model = "n25q256a",
.spi_model = "mx25l25635e",
.num_cs = 1,
+ .i2c_init = ast2500_evb_i2c_init,
},
[ROMULUS_BMC] = {
.soc_name = "ast2500-a1",
@@ -223,9 +229,22 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+ if (cfg->i2c_init) {
+ cfg->i2c_init(bmc);
+ }
+
arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
}
+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
+{
+ AspeedSoCState *soc = &bmc->soc;
+
+ /* The palmetto platform expects a ds3231 RTC but a ds1338 is
+ * enough to provide basic RTC features. Alarms will be missing */
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
+}
+
static void palmetto_bmc_init(MachineState *machine)
{
aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
@@ -250,6 +269,14 @@ static const TypeInfo palmetto_bmc_type = {
.class_init = palmetto_bmc_class_init,
};
+static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
+{
+ AspeedSoCState *soc = &bmc->soc;
+
+ /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
+}
+
static void ast2500_evb_init(MachineState *machine)
{
aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1,2,3} device model
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
` (3 preceding siblings ...)
2017-05-15 5:51 ` [Qemu-devel] [PATCH 4/6] aspeed: add some I2C devices to the Aspeed machines Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-06-02 10:51 ` [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1, 2, 3} " Peter Maydell
2017-05-15 5:51 ` [Qemu-devel] [PATCH 6/6] aspeed: add a temp sensor device on I2C bus 3 Cédric Le Goater
2017-06-01 16:18 ` [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Peter Maydell
6 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
Largely inspired by the TMP105 temperature sensor, here is a model for
the TMP42{1,2,3} temperature sensors.
Specs can be found here :
http://www.ti.com/lit/gpn/tmp421
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Changes since initial version:
- simplified tmp421_tx() as tmp421 does not need to support 2 bytes
writes.
- extended tmp421_read() to support 2 bytes reads
default-configs/arm-softmmu.mak | 1 +
hw/misc/Makefile.objs | 1 +
hw/misc/tmp421.c | 401 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 403 insertions(+)
create mode 100644 hw/misc/tmp421.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 78d7af03a2e8..93e995d31892 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -15,6 +15,7 @@ CONFIG_TWL92230=y
CONFIG_TSC2005=y
CONFIG_LM832X=y
CONFIG_TMP105=y
+CONFIG_TMP421=y
CONFIG_STELLARIS=y
CONFIG_STELLARIS_INPUT=y
CONFIG_STELLARIS_ENET=y
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c8b489390f7e..20198466f070 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -1,6 +1,7 @@
common-obj-$(CONFIG_APPLESMC) += applesmc.o
common-obj-$(CONFIG_MAX111X) += max111x.o
common-obj-$(CONFIG_TMP105) += tmp105.o
+common-obj-$(CONFIG_TMP421) += tmp421.o
common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
common-obj-$(CONFIG_SGA) += sga.o
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
new file mode 100644
index 000000000000..a57cf93f1658
--- /dev/null
+++ b/hw/misc/tmp421.c
@@ -0,0 +1,401 @@
+/*
+ * Texas Instruments TMP421 temperature sensor.
+ *
+ * Copyright (c) 2016 IBM Corporation.
+ *
+ * Largely inspired by :
+ *
+ * Texas Instruments TMP105 temperature sensor.
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+/* Manufacturer / Device ID's */
+#define TMP421_MANUFACTURER_ID 0x55
+#define TMP421_DEVICE_ID 0x21
+#define TMP422_DEVICE_ID 0x22
+#define TMP423_DEVICE_ID 0x23
+
+typedef struct DeviceInfo {
+ int model;
+ const char *name;
+} DeviceInfo;
+
+static const DeviceInfo devices[] = {
+ { TMP421_DEVICE_ID, "tmp421" },
+ { TMP422_DEVICE_ID, "tmp422" },
+ { TMP423_DEVICE_ID, "tmp423" },
+};
+
+typedef struct TMP421State {
+ /*< private >*/
+ I2CSlave i2c;
+ /*< public >*/
+
+ int16_t temperature[4];
+
+ uint8_t status;
+ uint8_t config[2];
+ uint8_t rate;
+
+ uint8_t len;
+ uint8_t buf[2];
+ uint8_t pointer;
+
+} TMP421State;
+
+typedef struct TMP421Class {
+ I2CSlaveClass parent_class;
+ DeviceInfo *dev;
+} TMP421Class;
+
+#define TYPE_TMP421 "tmp421-generic"
+#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
+
+#define TMP421_CLASS(klass) \
+ OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
+#define TMP421_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
+
+/* the TMP421 registers */
+#define TMP421_STATUS_REG 0x08
+#define TMP421_STATUS_BUSY (1 << 7)
+#define TMP421_CONFIG_REG_1 0x09
+#define TMP421_CONFIG_RANGE (1 << 2)
+#define TMP421_CONFIG_SHUTDOWN (1 << 6)
+#define TMP421_CONFIG_REG_2 0x0A
+#define TMP421_CONFIG_RC (1 << 2)
+#define TMP421_CONFIG_LEN (1 << 3)
+#define TMP421_CONFIG_REN (1 << 4)
+#define TMP421_CONFIG_REN2 (1 << 5)
+#define TMP421_CONFIG_REN3 (1 << 6)
+
+#define TMP421_CONVERSION_RATE_REG 0x0B
+#define TMP421_ONE_SHOT 0x0F
+
+#define TMP421_RESET 0xFC
+#define TMP421_MANUFACTURER_ID_REG 0xFE
+#define TMP421_DEVICE_ID_REG 0xFF
+
+#define TMP421_TEMP_MSB0 0x00
+#define TMP421_TEMP_MSB1 0x01
+#define TMP421_TEMP_MSB2 0x02
+#define TMP421_TEMP_MSB3 0x03
+#define TMP421_TEMP_LSB0 0x10
+#define TMP421_TEMP_LSB1 0x11
+#define TMP421_TEMP_LSB2 0x12
+#define TMP421_TEMP_LSB3 0x13
+
+static const int32_t mins[2] = { -40000, -55000 };
+static const int32_t maxs[2] = { 127000, 150000 };
+
+static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ TMP421State *s = TMP421(obj);
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+ int offset = ext_range * 64 * 256;
+ int64_t value;
+ int tempid;
+
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
+ error_setg(errp, "error reading %s: %m", name);
+ return;
+ }
+
+ if (tempid >= 4 || tempid < 0) {
+ error_setg(errp, "error reading %s", name);
+ return;
+ }
+
+ value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
+
+ visit_type_int(v, name, &value, errp);
+}
+
+/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8
+ * fixed point, so units are 1/256 centigrades. A simple ratio will do.
+ */
+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ TMP421State *s = TMP421(obj);
+ Error *local_err = NULL;
+ int64_t temp;
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+ int offset = ext_range * 64 * 256;
+ int tempid;
+
+ visit_type_int(v, name, &temp, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
+ error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
+ temp / 1000, temp % 1000);
+ return;
+ }
+
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
+ error_setg(errp, "error reading %s: %m", name);
+ return;
+ }
+
+ if (tempid >= 4 || tempid < 0) {
+ error_setg(errp, "error reading %s", name);
+ return;
+ }
+
+ s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
+}
+
+static void tmp421_read(TMP421State *s)
+{
+ TMP421Class *sc = TMP421_GET_CLASS(s);
+
+ s->len = 0;
+
+ switch (s->pointer) {
+ case TMP421_MANUFACTURER_ID_REG:
+ s->buf[s->len++] = TMP421_MANUFACTURER_ID;
+ break;
+ case TMP421_DEVICE_ID_REG:
+ s->buf[s->len++] = sc->dev->model;
+ break;
+ case TMP421_CONFIG_REG_1:
+ s->buf[s->len++] = s->config[0];
+ break;
+ case TMP421_CONFIG_REG_2:
+ s->buf[s->len++] = s->config[1];
+ break;
+ case TMP421_CONVERSION_RATE_REG:
+ s->buf[s->len++] = s->rate;
+ break;
+ case TMP421_STATUS_REG:
+ s->buf[s->len++] = s->status;
+ break;
+
+ /* FIXME: check for channel enablement in config registers */
+ case TMP421_TEMP_MSB0:
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB1:
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB2:
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB3:
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB0:
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB1:
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB2:
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB3:
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+ break;
+ }
+}
+
+static void tmp421_reset(I2CSlave *i2c);
+
+static void tmp421_write(TMP421State *s)
+{
+ switch (s->pointer) {
+ case TMP421_CONVERSION_RATE_REG:
+ s->rate = s->buf[0];
+ break;
+ case TMP421_CONFIG_REG_1:
+ s->config[0] = s->buf[0];
+ break;
+ case TMP421_CONFIG_REG_2:
+ s->config[1] = s->buf[0];
+ break;
+ case TMP421_RESET:
+ tmp421_reset(I2C_SLAVE(s));
+ break;
+ }
+}
+
+static int tmp421_rx(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (s->len < 2) {
+ return s->buf[s->len++];
+ } else {
+ return 0xff;
+ }
+}
+
+static int tmp421_tx(I2CSlave *i2c, uint8_t data)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (s->len == 0) {
+ /* first byte is the register pointer for a read or write
+ * operation */
+ s->pointer = data;
+ s->len++;
+ } else if (s->len == 1) {
+ /* second byte is the data to write. The device only supports
+ * one byte writes */
+ s->buf[0] = data;
+ tmp421_write(s);
+ }
+
+ return 0;
+}
+
+static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (event == I2C_START_RECV) {
+ tmp421_read(s);
+ }
+
+ s->len = 0;
+ return 0;
+}
+
+static const VMStateDescription vmstate_tmp421 = {
+ .name = "TMP421",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(len, TMP421State),
+ VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
+ VMSTATE_UINT8(pointer, TMP421State),
+ VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
+ VMSTATE_UINT8(status, TMP421State),
+ VMSTATE_UINT8(rate, TMP421State),
+ VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
+ VMSTATE_I2C_SLAVE(i2c, TMP421State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void tmp421_reset(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+ TMP421Class *sc = TMP421_GET_CLASS(s);
+
+ memset(s->temperature, 0, sizeof(s->temperature));
+ s->pointer = 0;
+
+ s->config[0] = 0; /* TMP421_CONFIG_RANGE */
+
+ /* resistance correction and channel enablement */
+ switch (sc->dev->model) {
+ case TMP421_DEVICE_ID:
+ s->config[1] = 0x1c;
+ break;
+ case TMP422_DEVICE_ID:
+ s->config[1] = 0x3c;
+ break;
+ case TMP423_DEVICE_ID:
+ s->config[1] = 0x7c;
+ break;
+ }
+
+ s->rate = 0x7; /* 8Hz */
+ s->status = 0;
+}
+
+static int tmp421_init(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+
+ tmp421_reset(&s->i2c);
+
+ return 0;
+}
+
+static void tmp421_initfn(Object *obj)
+{
+ object_property_add(obj, "temperature0", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature1", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature2", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature3", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+}
+
+static void tmp421_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+ TMP421Class *sc = TMP421_CLASS(klass);
+
+ k->init = tmp421_init;
+ k->event = tmp421_event;
+ k->recv = tmp421_rx;
+ k->send = tmp421_tx;
+ dc->vmsd = &vmstate_tmp421;
+ sc->dev = (DeviceInfo *) data;
+}
+
+static const TypeInfo tmp421_info = {
+ .name = TYPE_TMP421,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(TMP421State),
+ .instance_init = tmp421_initfn,
+ .class_init = tmp421_class_init,
+};
+
+static void tmp421_register_types(void)
+{
+ int i;
+
+ type_register_static(&tmp421_info);
+ for (i = 0; i < ARRAY_SIZE(devices); ++i) {
+ TypeInfo ti = {
+ .name = devices[i].name,
+ .parent = TYPE_TMP421,
+ .class_init = tmp421_class_init,
+ .class_data = (void *) &devices[i],
+ };
+ type_register(&ti);
+ }
+}
+
+type_init(tmp421_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1, 2, 3} device model
2017-05-15 5:51 ` [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1,2,3} device model Cédric Le Goater
@ 2017-06-02 10:51 ` Peter Maydell
2017-06-02 12:01 ` Cédric Le Goater
0 siblings, 1 reply; 10+ messages in thread
From: Peter Maydell @ 2017-06-02 10:51 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-arm, QEMU Developers
On 15 May 2017 at 06:51, Cédric Le Goater <clg@kaod.org> wrote:
> Largely inspired by the TMP105 temperature sensor, here is a model for
> the TMP42{1,2,3} temperature sensors.
>
> Specs can be found here :
>
> http://www.ti.com/lit/gpn/tmp421
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This turns out to segfault on OSX and BSD...
> +static void tmp421_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
> + TMP421Class *sc = TMP421_CLASS(klass);
> +
> + k->init = tmp421_init;
> + k->event = tmp421_event;
> + k->recv = tmp421_rx;
> + k->send = tmp421_tx;
> + dc->vmsd = &vmstate_tmp421;
> + sc->dev = (DeviceInfo *) data;
...because this write to sc->dev is off the end of a
malloced block. You can see this with valgrind on Linux:
$ valgrind ./build/x86/aarch64-softmmu/qemu-system-aarch64
==14009== Memcheck, a memory error detector
[...]
==14009== Invalid write of size 8
==14009== at 0x67D3D9: tmp421_class_init (tmp421.c:374)
==14009== by 0x80CD51: type_initialize (object.c:334)
==14009== by 0x80CABC: type_initialize (object.c:286)
==14009== by 0x80DF49: object_class_foreach_tramp (object.c:805)
==14009== by 0x1B7AE33F: g_hash_table_foreach (in
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
==14009== by 0x80E028: object_class_foreach (object.c:827)
==14009== by 0x80E1F7: object_class_get_list (object.c:881)
==14009== by 0x5500A8: find_default_machine (vl.c:1488)
==14009== by 0x554039: select_machine (vl.c:2745)
==14009== by 0x55730E: main (vl.c:4091)
==14009== Address 0x2b4e7cd0 is 0 bytes after a block of size 224 alloc'd
==14009== at 0x4C2FB55: calloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==14009== by 0x1B7C4770: g_malloc0 (in
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
==14009== by 0x80CA8A: type_initialize (object.c:282)
==14009== by 0x80CABC: type_initialize (object.c:286)
==14009== by 0x80DF49: object_class_foreach_tramp (object.c:805)
==14009== by 0x1B7AE33F: g_hash_table_foreach (in
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
==14009== by 0x80E028: object_class_foreach (object.c:827)
==14009== by 0x80E1F7: object_class_get_list (object.c:881)
==14009== by 0x5500A8: find_default_machine (vl.c:1488)
==14009== by 0x554039: select_machine (vl.c:2745)
==14009== by 0x55730E: main (vl.c:4091)
==14009==
> +}
> +
> +static const TypeInfo tmp421_info = {
> + .name = TYPE_TMP421,
> + .parent = TYPE_I2C_SLAVE,
> + .instance_size = sizeof(TMP421State),
> + .instance_init = tmp421_initfn,
> + .class_init = tmp421_class_init,
...which is because this TypeInfo doesn't set the
.class_size field, so only sizeof(I2CSlaveClass) is
allocated, not sizeof(TMP421Class).
(http://wiki.qemu.org/Documentation/QOMConventions
lists this as one of the things you need to do for a class
that has a class struct).
> +};
> +
> +static void tmp421_register_types(void)
> +{
> + int i;
> +
> + type_register_static(&tmp421_info);
> + for (i = 0; i < ARRAY_SIZE(devices); ++i) {
> + TypeInfo ti = {
> + .name = devices[i].name,
> + .parent = TYPE_TMP421,
> + .class_init = tmp421_class_init,
> + .class_data = (void *) &devices[i],
This TypeInfo is a bit odd too, looking more closely at it.
It defines a type that's a subclass of TYPE_TMP421, but which
has a class_init method that's the same function as TYPE_TMP421's
class_init method. That means we call it twice for the same
class, which doesn't seem right.
> + };
> + type_register(&ti);
> + }
> +}
> +
> +type_init(tmp421_register_types)
> --
> 2.7.4
I'm going to drop this patch and the next one from my arm
queue, but leave 1-4 in.
thanks
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1, 2, 3} device model
2017-06-02 10:51 ` [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1, 2, 3} " Peter Maydell
@ 2017-06-02 12:01 ` Cédric Le Goater
0 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-06-02 12:01 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, QEMU Developers
On 06/02/2017 12:51 PM, Peter Maydell wrote:
> On 15 May 2017 at 06:51, Cédric Le Goater <clg@kaod.org> wrote:
>> Largely inspired by the TMP105 temperature sensor, here is a model for
>> the TMP42{1,2,3} temperature sensors.
>>
>> Specs can be found here :
>>
>> http://www.ti.com/lit/gpn/tmp421
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> This turns out to segfault on OSX and BSD...
>
>> +static void tmp421_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
>> + TMP421Class *sc = TMP421_CLASS(klass);
>> +
>> + k->init = tmp421_init;
>> + k->event = tmp421_event;
>> + k->recv = tmp421_rx;
>> + k->send = tmp421_tx;
>> + dc->vmsd = &vmstate_tmp421;
>> + sc->dev = (DeviceInfo *) data;
>
> ...because this write to sc->dev is off the end of a
> malloced block. You can see this with valgrind on Linux:
>
> $ valgrind ./build/x86/aarch64-softmmu/qemu-system-aarch64
> ==14009== Memcheck, a memory error detector
> [...]
> ==14009== Invalid write of size 8
> ==14009== at 0x67D3D9: tmp421_class_init (tmp421.c:374)
> ==14009== by 0x80CD51: type_initialize (object.c:334)
> ==14009== by 0x80CABC: type_initialize (object.c:286)
> ==14009== by 0x80DF49: object_class_foreach_tramp (object.c:805)
> ==14009== by 0x1B7AE33F: g_hash_table_foreach (in
> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
> ==14009== by 0x80E028: object_class_foreach (object.c:827)
> ==14009== by 0x80E1F7: object_class_get_list (object.c:881)
> ==14009== by 0x5500A8: find_default_machine (vl.c:1488)
> ==14009== by 0x554039: select_machine (vl.c:2745)
> ==14009== by 0x55730E: main (vl.c:4091)
> ==14009== Address 0x2b4e7cd0 is 0 bytes after a block of size 224 alloc'd
> ==14009== at 0x4C2FB55: calloc (in
> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
> ==14009== by 0x1B7C4770: g_malloc0 (in
> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
> ==14009== by 0x80CA8A: type_initialize (object.c:282)
> ==14009== by 0x80CABC: type_initialize (object.c:286)
> ==14009== by 0x80DF49: object_class_foreach_tramp (object.c:805)
> ==14009== by 0x1B7AE33F: g_hash_table_foreach (in
> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
> ==14009== by 0x80E028: object_class_foreach (object.c:827)
> ==14009== by 0x80E1F7: object_class_get_list (object.c:881)
> ==14009== by 0x5500A8: find_default_machine (vl.c:1488)
> ==14009== by 0x554039: select_machine (vl.c:2745)
> ==14009== by 0x55730E: main (vl.c:4091)
> ==14009==
>
>> +}
>> +
>> +static const TypeInfo tmp421_info = {
>> + .name = TYPE_TMP421,
>> + .parent = TYPE_I2C_SLAVE,
>> + .instance_size = sizeof(TMP421State),
>> + .instance_init = tmp421_initfn,
>> + .class_init = tmp421_class_init,
>
> ...which is because this TypeInfo doesn't set the
> .class_size field, so only sizeof(I2CSlaveClass) is
> allocated, not sizeof(TMP421Class).
>
> (http://wiki.qemu.org/Documentation/QOMConventions
> lists this as one of the things you need to do for a class
> that has a class struct).
>
>> +};
>> +
>> +static void tmp421_register_types(void)
>> +{
>> + int i;
>> +
>> + type_register_static(&tmp421_info);
>> + for (i = 0; i < ARRAY_SIZE(devices); ++i) {
>> + TypeInfo ti = {
>> + .name = devices[i].name,
>> + .parent = TYPE_TMP421,
>> + .class_init = tmp421_class_init,
>> + .class_data = (void *) &devices[i],
>
> This TypeInfo is a bit odd too, looking more closely at it.
> It defines a type that's a subclass of TYPE_TMP421, but which
> has a class_init method that's the same function as TYPE_TMP421's
> class_init method. That means we call it twice for the same
> class, which doesn't seem right.
>
>> + };
>> + type_register(&ti);
>> + }
>> +}
>> +
>> +type_init(tmp421_register_types)
>> --
>> 2.7.4
>
> I'm going to drop this patch and the next one from my arm
> queue, but leave 1-4 in.
OK. I should be able to fix it before 2.10.
I would also like to spend some time on the rx8900 model Alastair
wrote. It would give an RTC to the romulus machine.
Thanks for the tests and analysis.
C.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 6/6] aspeed: add a temp sensor device on I2C bus 3
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
` (4 preceding siblings ...)
2017-05-15 5:51 ` [Qemu-devel] [PATCH 5/6] hw/misc: add a TMP42{1,2,3} device model Cédric Le Goater
@ 2017-05-15 5:51 ` Cédric Le Goater
2017-06-01 16:18 ` [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Peter Maydell
6 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2017-05-15 5:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
Temperatures can be changed from the monitor with :
(qemu) qom-set /machine/unattached/device[2] temperature0 12000
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e824ea87a9af..155eeb242b8a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -239,10 +239,19 @@ static void aspeed_board_init(MachineState *machine,
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
+ DeviceState *dev;
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
* enough to provide basic RTC features. Alarms will be missing */
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
+
+ /* add a TMP423 temperature sensor */
+ dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
+ "tmp423", 0x4c);
+ object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
+ object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
+ object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
+ object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
}
static void palmetto_bmc_init(MachineState *machine)
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes
2017-05-15 5:51 [Qemu-devel] [PATCH 0/6] aspeed: I2C controller fixes Cédric Le Goater
` (5 preceding siblings ...)
2017-05-15 5:51 ` [Qemu-devel] [PATCH 6/6] aspeed: add a temp sensor device on I2C bus 3 Cédric Le Goater
@ 2017-06-01 16:18 ` Peter Maydell
6 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2017-06-01 16:18 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-arm, QEMU Developers
On 15 May 2017 at 06:51, Cédric Le Goater <clg@kaod.org> wrote:
> Hello,
>
> The new Linux driver for the Aspeed I2C controller revealed some
> serious limitations in the QEMU model. This series fixes these issues
> and also adds a couple of well-know I2C devices to the Aspeed
> machines.
>
> The QEMU model now supports the recent Linux driver and the older one.
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread