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From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH Risu v3 3/4] risugen, risugen_ppc64.pm: Add support ppc64 (big-endian)
Date: Thu, 25 May 2017 16:10:22 -0300	[thread overview]
Message-ID: <1495739423-32326-4-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com>

This commit adds an option to risugen in order to give the opportunity
to generated big-endian instructions. By passing --be, users force
risugen to generated big-endian instructions for ppc64.

./risugen --be --numinsns 1000 --pattern "ADD" ppc64.risu test.bin
./risugen --numinsns 1000 --pattern "ADD" ppc64.risu test.bin

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen          | 6 +++++-
 risugen_ppc64.pm | 4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/risugen b/risugen
index 6aad626..8b20425 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +264,7 @@ Valid options:
                    a general set you have excluded.
      --no-fp      : disable floating point: no fp init, randomization etc.
                    Useful to test before support for FP is available.
+    --be         : generate instructions in Big-Endian byte order (ppc64 only).
     --help       : print this message
 EOT
 }
@@ -274,6 +275,7 @@ sub main()
     my $condprob = 0;
     my $fpscr = 0;
     my $fp_enabled = 1;
+    my $big_endian = 0;
     my ($infile, $outfile);
 
     GetOptions( "help" => sub { usage(); exit(0); },
@@ -287,6 +289,7 @@ sub main()
                         die "Value \"$condprob\" invalid for option condprob (must be between 0 and 1)\n";
                     }
                 },
+                "be" => sub { $big_endian = 1; },
                 "no-fp" => sub { $fp_enabled = 0; },
         ) or return 1;
     # allow "--pattern re,re" and "--pattern re --pattern re"
@@ -317,7 +320,8 @@ sub main()
         'not_pattern_re' => \@not_pattern_re,
         'details' => \%insn_details,
         'arch' => $full_arch[0],
-        'subarch' => $full_arch[1] || ''
+        'subarch' => $full_arch[1] || '',
+        'bigendian' => $big_endian
     );
 
     write_test_code(\%params);
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 1a3cd59..c0e71cf 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -375,6 +375,10 @@ sub write_test_code($)
     my @not_pattern_re = @{ $params->{ 'not_pattern_re' } };
     my %insn_details = %{ $params->{ 'details' } };
 
+    if ($params->{ 'bigendian' } eq 1) {
+        set_endian(1);
+    }
+
     open_bin($outfile);
 
     # convert from probability that insn will be conditional to
-- 
2.7.4

  parent reply	other threads:[~2017-05-25 19:11 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-25 19:10 [Qemu-devel] [PATCH Risu v3 0/4] PPC64 Improvements Jose Ricardo Ziviani
2017-05-25 19:10 ` [Qemu-devel] [PATCH Risu v3 1/4] risugen_ppc64: Load random 128-bit data to vector registers Jose Ricardo Ziviani
2017-05-25 19:10 ` [Qemu-devel] [PATCH Risu v3 2/4] configure: Add initial support to PPC64 (big endian) Jose Ricardo Ziviani
2017-05-25 19:10 ` Jose Ricardo Ziviani [this message]
2017-05-25 19:10 ` [Qemu-devel] [PATCH Risu v3 4/4] build: Add support to PowerPC BE and remove ARCH Jose Ricardo Ziviani
2017-05-30 14:27   ` Peter Maydell
2017-05-30 18:55     ` joserz

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