* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2014-05-13 15:31 Peter Maydell
2014-05-15 16:07 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2014-05-13 15:31 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Flushing the target-arm queue (whose contents are mostly a bunch of
simple patches from me).
thanks
-- PMM
The following changes since commit cd2b9b86803e46a09cf239afc44413884efa53f4:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20140512' into staging (2014-05-13 13:16:37 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140513
for you to fetch changes up to 89f26e6b7b5e5c9657f2abd6ef5a336bea11add2:
hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO (2014-05-13 16:09:39 +0100)
----------------------------------------------------------------
target-arm queue:
* update libvixl to 1.4
* remove version_minimum_id_old from ARM devices
* stellaris_enet tx/rx/migration overhaul
* various minor fixes for coverity issues
----------------------------------------------------------------
Juan Quintela (1):
savevm: Remove all the unneeded version_minimum_id_old (arm)
Peter Maydell (16):
disas/libvixl: Update to libvixl 1.4
hw/net/stellaris_enet: Restructure tx_fifo code to avoid buffer overrun
hw/net/stellaris_enet: Correct handling of packet padding
hw/net/stellaris_enet: Rewrite tx fifo handling code
hw/net/stellaris_enet: Correctly implement the TR and THR registers
hw/net/stellaris_enet: Fix debug format strings
hw/net/stellaris_enet: Get rid of rx_fifo pointer
hw/net/stellaris_enet: Convert to vmstate
target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged
hw/intc/allwinner-a10-pic: Add missing 'break'
hw/net/cadence_gem: Remove dead code
hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REG
hw/dma/omap_dma: Add (uint32_t) casts when shifting uint16_t by 16
hw/timer/exynos4210_mct: Avoid overflow in exynos4210_ltick_recalc_count
hw/arm/stellaris: Correct handling of GPTM TAR register
hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO
disas/libvixl/a64/assembler-a64.h | 451 +++++++++++++++++++++-------------
disas/libvixl/a64/constants-a64.h | 36 ++-
disas/libvixl/a64/decoder-a64.cc | 36 +--
disas/libvixl/a64/disasm-a64.cc | 189 ++++++++------
disas/libvixl/a64/disasm-a64.h | 1 +
disas/libvixl/a64/instructions-a64.cc | 32 +--
disas/libvixl/a64/instructions-a64.h | 56 +++--
disas/libvixl/globals.h | 42 +++-
disas/libvixl/platform.h | 4 +-
disas/libvixl/utils.cc | 37 +--
disas/libvixl/utils.h | 86 ++++++-
hw/arm/highbank.c | 1 -
hw/arm/musicpal.c | 8 -
hw/arm/omap1.c | 4 +-
hw/arm/pxa2xx.c | 19 +-
hw/arm/pxa2xx_gpio.c | 3 +-
hw/arm/pxa2xx_pic.c | 1 -
hw/arm/spitz.c | 12 +-
hw/arm/stellaris.c | 25 +-
hw/arm/strongarm.c | 6 -
hw/arm/z2.c | 2 -
hw/audio/lm4549.c | 5 +-
hw/audio/marvell_88w8618.c | 1 -
hw/audio/pl041.c | 9 +-
hw/audio/wm8750.c | 3 +-
hw/block/ecc.c | 3 +-
hw/block/nand.c | 3 +-
hw/block/onenand.c | 1 -
hw/char/cadence_uart.c | 1 -
hw/char/digic-uart.c | 1 -
hw/char/exynos4210_uart.c | 2 -
hw/char/imx_serial.c | 1 -
hw/char/pl011.c | 3 +-
hw/display/ads7846.c | 3 +-
hw/display/exynos4210_fimd.c | 4 +-
hw/display/pxa2xx_lcd.c | 6 +-
hw/display/ssd0303.c | 3 +-
hw/dma/omap_dma.c | 12 +-
hw/dma/pl330.c | 5 -
hw/dma/pxa2xx_dma.c | 2 -
hw/gpio/max7310.c | 3 +-
hw/gpio/zaurus.c | 3 +-
hw/input/lm832x.c | 3 +-
hw/input/pxa2xx_keypad.c | 3 +-
hw/input/stellaris_input.c | 6 +-
hw/intc/allwinner-a10-pic.c | 2 +-
hw/intc/armv7m_nvic.c | 3 +-
hw/intc/exynos4210_combiner.c | 2 -
hw/intc/exynos4210_gic.c | 1 -
hw/intc/imx_avic.c | 1 -
hw/misc/exynos4210_pmu.c | 2 +-
hw/misc/imx_ccm.c | 1 -
hw/misc/max111x.c | 3 +-
hw/misc/mst_fpga.c | 11 +-
hw/misc/omap_gpmc.c | 4 +
hw/misc/tmp105.c | 3 +-
hw/misc/zynq_slcr.c | 3 +-
hw/net/cadence_gem.c | 11 +-
hw/net/smc91c111.c | 2 +-
hw/net/stellaris_enet.c | 312 +++++++++++++----------
hw/net/xgmac.c | 2 +-
hw/ssi/pl022.c | 3 +-
hw/ssi/ssi.c | 3 +-
hw/ssi/xilinx_spi.c | 1 -
hw/ssi/xilinx_spips.c | 1 -
hw/timer/allwinner-a10-pit.c | 1 -
hw/timer/arm_timer.c | 6 +-
hw/timer/cadence_ttc.c | 2 -
hw/timer/digic-timer.c | 1 -
hw/timer/ds1338.c | 1 -
hw/timer/exynos4210_mct.c | 10 +-
hw/timer/exynos4210_pwm.c | 2 -
hw/timer/exynos4210_rtc.c | 1 -
hw/timer/imx_epit.c | 3 +-
hw/timer/imx_gpt.c | 3 +-
hw/timer/pxa2xx_timer.c | 3 -
hw/timer/twl92230.c | 6 +-
target-arm/helper.c | 7 +
target-arm/machine.c | 5 -
util/fifo8.c | 3 +-
80 files changed, 905 insertions(+), 657 deletions(-)
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2014-05-13 15:31 Peter Maydell
@ 2014-05-15 16:07 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2014-05-15 16:07 UTC (permalink / raw)
To: Anthony Liguori; +Cc: QEMU Developers
On 13 May 2014 16:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> Flushing the target-arm queue (whose contents are mostly a bunch of
> simple patches from me).
>
> thanks
> -- PMM
>
> The following changes since commit cd2b9b86803e46a09cf239afc44413884efa53f4:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20140512' into staging (2014-05-13 13:16:37 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140513
>
> for you to fetch changes up to 89f26e6b7b5e5c9657f2abd6ef5a336bea11add2:
>
> hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO (2014-05-13 16:09:39 +0100)
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2015-04-27 15:20 Peter Maydell
2015-04-28 10:33 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2015-04-27 15:20 UTC (permalink / raw)
To: qemu-devel
2.4 is not officially open yet (I'm waiting for Michael to post
the actual 2.3 release announcement) but this is lined up
ready, since I'd like to get the memory attributes patches in
sooner rather than later to reduce the risk of conflicts.
-- PMM
The following changes since commit e1a5476354d396773e4c555f126d752d4ae58fa9:
Open 2.4 development tree (2015-04-25 22:05:07 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150427
for you to fetch changes up to 4eb276408363aef5435a72a8e818f24220b5edd0:
Allow ARMv8 SCR.SMD updates (2015-04-26 16:49:26 +0100)
----------------------------------------------------------------
target-arm queue:
* memory system updates to support transaction attributes
* set user-mode and secure attributes for accesses made by ARM CPUs
* rename c1_coproc to cpacr_el1
* adjust id_aa64pfr0 when has_el3 CPU property disabled
* allow ARMv8 SCR.SMD updates
----------------------------------------------------------------
Greg Bellows (1):
Allow ARMv8 SCR.SMD updates
Peter Maydell (14):
memory: Define API for MemoryRegionOps to take attrs and return status
memory: Replace io_mem_read/write with memory_region_dispatch_read/write
Make CPU iotlb a structure rather than a plain hwaddr
Add MemTxAttrs to the IOTLB
exec.c: Convert subpage memory ops to _with_attrs
exec.c: Make address_space_rw take transaction attributes
exec.c: Add new address_space_ld*/st* functions
exec.c: Capture the memory attributes for a watchpoint hit
Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
target-arm: Honour NS bits in page tables
target-arm: Use correct memory attributes for page table walks
target-arm: Add user-mode transaction attribute
target-arm: Use attribute info to handle user-only watchpoints
target-arm: Check watchpoints against CPU security state
Sergey Fedorov (2):
target-arm: rename c1_coproc to cpacr_el1
target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
cputlb.c | 22 +-
dma-helpers.c | 3 +-
exec.c | 426 ++++++++++++++++++++++++++++++--------
hw/alpha/dp264.c | 9 +-
hw/alpha/typhoon.c | 3 +-
hw/arm/boot.c | 6 +-
hw/arm/highbank.c | 12 +-
hw/arm/pxa2xx.c | 2 +-
hw/dma/pl080.c | 20 +-
hw/dma/sun4m_iommu.c | 3 +-
hw/i386/intel_iommu.c | 3 +-
hw/mips/mips_jazz.c | 6 +-
hw/pci-host/apb.c | 3 +-
hw/pci-host/prep.c | 6 +-
hw/pci/msi.c | 3 +-
hw/pci/msix.c | 3 +-
hw/s390x/css.c | 19 +-
hw/s390x/s390-pci-bus.c | 9 +-
hw/s390x/s390-pci-inst.c | 10 +-
hw/s390x/s390-virtio-bus.c | 73 ++++---
hw/s390x/s390-virtio.c | 4 +-
hw/s390x/virtio-ccw.c | 87 +++++---
hw/sh4/r2d.c | 6 +-
hw/timer/hpet.c | 5 +-
hw/vfio/pci.c | 18 +-
include/exec/cpu-defs.h | 15 +-
include/exec/exec-all.h | 7 +-
include/exec/memattrs.h | 45 ++++
include/exec/memory.h | 151 +++++++++++++-
include/qom/cpu.h | 2 +
include/sysemu/dma.h | 3 +-
ioport.c | 16 +-
kvm-all.c | 3 +-
memory.c | 204 +++++++++++-------
monitor.c | 3 +-
scripts/coverity-model.c | 8 +-
softmmu_template.h | 38 ++--
target-arm/cpu.c | 7 +-
target-arm/cpu.h | 4 +-
target-arm/helper.c | 137 +++++++++---
target-arm/op_helper.c | 29 +--
target-i386/arch_memory_mapping.c | 15 +-
42 files changed, 1086 insertions(+), 362 deletions(-)
create mode 100644 include/exec/memattrs.h
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2015-04-27 15:20 Peter Maydell
@ 2015-04-28 10:33 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2015-04-28 10:33 UTC (permalink / raw)
To: QEMU Developers
On 27 April 2015 at 16:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> 2.4 is not officially open yet (I'm waiting for Michael to post
> the actual 2.3 release announcement) but this is lined up
> ready, since I'd like to get the memory attributes patches in
> sooner rather than later to reduce the risk of conflicts.
>
> -- PMM
>
> The following changes since commit e1a5476354d396773e4c555f126d752d4ae58fa9:
>
> Open 2.4 development tree (2015-04-25 22:05:07 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150427
>
> for you to fetch changes up to 4eb276408363aef5435a72a8e818f24220b5edd0:
>
> Allow ARMv8 SCR.SMD updates (2015-04-26 16:49:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * memory system updates to support transaction attributes
> * set user-mode and secure attributes for accesses made by ARM CPUs
> * rename c1_coproc to cpacr_el1
> * adjust id_aa64pfr0 when has_el3 CPU property disabled
> * allow ARMv8 SCR.SMD updates
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2016-02-03 18:59 Peter Maydell
2016-02-04 12:50 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2016-02-03 18:59 UTC (permalink / raw)
To: qemu-devel
ARM queue -- most interesting thing here is the raspberry pi 2
board model.
thanks
-- PMM
The following changes since commit 87574621b18f86eab295a2c207e0b42c77b5dfa0:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20160203-1' into staging (2016-02-03 12:23:48 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160203
for you to fetch changes up to 1df7d1f9303aef9a2b1f703e887553416b7c0586:
raspi: add raspberry pi 2 machine (2016-02-03 15:00:47 +0000)
----------------------------------------------------------------
target-arm queue:
* virt-acpi-build: add always-on property for timer
* various fixes for EL2 and EL3 behaviour
* arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
* target-arm: Don't report presence of EL2 if it doesn't exist
* raspi: add raspberry pi 2 machine
----------------------------------------------------------------
Andrew Baumann (8):
bcm2835_mbox: add BCM2835 mailboxes
bcm2835_property: add bcm2835 property channel
bcm2835_ic: add bcm2835 interrupt controller
bcm2835_peripherals: add rollup device for bcm2835 peripherals
bcm2836_control: add bcm2836 ARM control logic
bcm2836: add bcm2836 SoC device
arm/boot: move highbank secure board setup code to common routine
raspi: add raspberry pi 2 machine
Andrew Jones (1):
virt-acpi-build: add always-on property for timer
Edgar E. Iglesias (4):
hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots
target-arm: Apply S2 MMU startlevel table size check to AArch64
target-arm: Rename check_s2_startlevel to check_s2_mmu_setup
target-arm: Implement the S2 MMU inputsize > pamax check
Igor Mammedov (1):
arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
Peter Maydell (3):
target-arm: Make various system registers visible to EL3
libvixl: Avoid std::abs() of 64-bit type
target-arm: Don't report presence of EL2 if it doesn't exist
default-configs/arm-softmmu.mak | 1 +
disas/libvixl/vixl/a64/disasm-a64.cc | 6 +-
hw/arm/Makefile.objs | 1 +
hw/arm/bcm2835_peripherals.c | 204 +++++++++++++++++++++
hw/arm/bcm2836.c | 165 +++++++++++++++++
hw/arm/boot.c | 53 ++++++
hw/arm/highbank.c | 37 +---
hw/arm/raspi.c | 152 ++++++++++++++++
hw/arm/virt-acpi-build.c | 28 +--
hw/intc/Makefile.objs | 1 +
hw/intc/bcm2835_ic.c | 236 +++++++++++++++++++++++++
hw/intc/bcm2836_control.c | 303 +++++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 2 +
hw/misc/bcm2835_mbox.c | 333 +++++++++++++++++++++++++++++++++++
hw/misc/bcm2835_property.c | 287 ++++++++++++++++++++++++++++++
include/hw/arm/arm.h | 5 +
include/hw/arm/bcm2835_peripherals.h | 42 +++++
include/hw/arm/bcm2836.h | 35 ++++
include/hw/arm/raspi_platform.h | 128 ++++++++++++++
include/hw/arm/virt-acpi-build.h | 1 -
include/hw/intc/bcm2835_ic.h | 33 ++++
include/hw/intc/bcm2836_control.h | 51 ++++++
include/hw/misc/bcm2835_mbox.h | 38 ++++
include/hw/misc/bcm2835_mbox_defs.h | 27 +++
include/hw/misc/bcm2835_property.h | 31 ++++
target-arm/cpu.c | 9 +
target-arm/helper.c | 94 +++++-----
27 files changed, 2199 insertions(+), 104 deletions(-)
create mode 100644 hw/arm/bcm2835_peripherals.c
create mode 100644 hw/arm/bcm2836.c
create mode 100644 hw/arm/raspi.c
create mode 100644 hw/intc/bcm2835_ic.c
create mode 100644 hw/intc/bcm2836_control.c
create mode 100644 hw/misc/bcm2835_mbox.c
create mode 100644 hw/misc/bcm2835_property.c
create mode 100644 include/hw/arm/bcm2835_peripherals.h
create mode 100644 include/hw/arm/bcm2836.h
create mode 100644 include/hw/arm/raspi_platform.h
create mode 100644 include/hw/intc/bcm2835_ic.h
create mode 100644 include/hw/intc/bcm2836_control.h
create mode 100644 include/hw/misc/bcm2835_mbox.h
create mode 100644 include/hw/misc/bcm2835_mbox_defs.h
create mode 100644 include/hw/misc/bcm2835_property.h
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2016-02-03 18:59 Peter Maydell
@ 2016-02-04 12:50 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2016-02-04 12:50 UTC (permalink / raw)
To: QEMU Developers
On 3 February 2016 at 18:59, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue -- most interesting thing here is the raspberry pi 2
> board model.
>
> thanks
> -- PMM
>
>
> The following changes since commit 87574621b18f86eab295a2c207e0b42c77b5dfa0:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20160203-1' into staging (2016-02-03 12:23:48 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160203
>
> for you to fetch changes up to 1df7d1f9303aef9a2b1f703e887553416b7c0586:
>
> raspi: add raspberry pi 2 machine (2016-02-03 15:00:47 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * virt-acpi-build: add always-on property for timer
> * various fixes for EL2 and EL3 behaviour
> * arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
> * target-arm: Don't report presence of EL2 if it doesn't exist
> * raspi: add raspberry pi 2 machine
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2016-03-30 14:57 Peter Maydell
2016-03-30 16:25 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2016-03-30 14:57 UTC (permalink / raw)
To: qemu-devel
Last lot of target-arm patches just sneaking under the wire:
* m25p80 (should be safe enough since not really used by anything)
* virt power key bugfix
* query-gic-capabilities QMP command
thanks
-- PMM
The following changes since commit b9c27e7ae6fb1387eafe858d8378ff14cd1c5b89:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-03-30 13:43:05 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160330
for you to fetch changes up to eefb90314f80c421899f8c42e59df7b80a27c93b:
arm: implement query-gic-capabilities (2016-03-30 15:48:27 +0100)
----------------------------------------------------------------
target-arm queue:
* virt: fix the virtual power button by adding a modelled
"key press for 100ms" device
* various improvements to m25p80 flash devices
* implement new QMP query-gic-capability command to let the
management layer know what versions of GIC we support
----------------------------------------------------------------
Marcin Krzeminski (11):
block: m25p80: Removed unused variable
block: m25p80: RESET_ENABLE and RESET_MEMORY commands
block: m25p80: Widen flags variable
block: m25p80: Extend address mode
block: m25p80: 4byte address mode
block: m25p80: Add configuration registers
block: m25p80: Dummy cycles for N25Q256/512
block: m25p80: Fast read and 4bytes commands
block: m25p80: Implemented FSR register
block: m25p80: n25q256a/n25q512a models
block: m25p80: at25128a/at25256a models
Peter Xu (4):
arm: qmp: add query-gic-capabilities interface
arm: enhance kvm_arm_create_scratch_host_vcpu
kvm: add kvm_device_supported() helper function
arm: implement query-gic-capabilities
Shannon Zhao (2):
hw/gpio: Add the emulation of gpio_key
ARM: Virt: Use gpio_key for power button
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 7 +-
hw/block/m25p80.c | 330 +++++++++++++++++++++++++++++++++++++---
hw/gpio/Makefile.objs | 1 +
hw/gpio/gpio_key.c | 104 +++++++++++++
include/sysemu/kvm.h | 9 ++
kvm-all.c | 15 ++
monitor.c | 8 +
qapi-schema.json | 36 +++++
qmp-commands.hx | 27 ++++
target-arm/Makefile.objs | 2 +-
target-arm/kvm.c | 14 +-
target-arm/kvm_arm.h | 7 +-
target-arm/monitor.c | 84 ++++++++++
14 files changed, 620 insertions(+), 25 deletions(-)
create mode 100644 hw/gpio/gpio_key.c
create mode 100644 target-arm/monitor.c
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2016-03-30 14:57 Peter Maydell
@ 2016-03-30 16:25 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2016-03-30 16:25 UTC (permalink / raw)
To: QEMU Developers
On 30 March 2016 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Last lot of target-arm patches just sneaking under the wire:
> * m25p80 (should be safe enough since not really used by anything)
> * virt power key bugfix
> * query-gic-capabilities QMP command
>
> thanks
> -- PMM
>
> The following changes since commit b9c27e7ae6fb1387eafe858d8378ff14cd1c5b89:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-03-30 13:43:05 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160330
>
> for you to fetch changes up to eefb90314f80c421899f8c42e59df7b80a27c93b:
>
> arm: implement query-gic-capabilities (2016-03-30 15:48:27 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * virt: fix the virtual power button by adding a modelled
> "key press for 100ms" device
> * various improvements to m25p80 flash devices
> * implement new QMP query-gic-capability command to let the
> management layer know what versions of GIC we support
Whoops, build failure for the linux-user targets. Fixup patch:
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 334074c..82cbe6b 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -1,5 +1,5 @@
obj-y += arm-semi.o
-obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o
+obj-$(CONFIG_SOFTMMU) += machine.o psci.o arch_dump.o monitor.o
obj-$(CONFIG_KVM) += kvm.o
obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
@@ -8,4 +8,4 @@ obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += neon_helper.o iwmmxt_helper.o
obj-y += gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
-obj-y += crypto_helper.o monitor.o
+obj-y += crypto_helper.o
thanks
-- PMM
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2017-06-13 14:06 Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable Peter Maydell
` (18 more replies)
0 siblings, 19 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
Target-arm queue...
thanks
-- PMM
The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613
for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5:
hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100)
----------------------------------------------------------------
target-arm queue:
* vITS: Support save/restore
* timer/aspeed: Fix timer enablement when reload is not set
* aspped: add temperature sensor device
* timer.h: Provide better monotonic time on ARM hosts
* exynos4210: various cleanups
* exynos4210: support system poweroff
----------------------------------------------------------------
Cédric Le Goater (3):
hw/misc: add a TMP42{1, 2, 3} device model
aspeed: add a temp sensor device on I2C bus 3
timer/aspeed: fix timer enablement when a reload is not set
Eric Auger (4):
kvm-all: Pass an error object to kvm_device_access
hw/intc/arm_gicv3_its: Implement state save/restore
hw/intc/arm_gicv3_kvm: Implement pending table save
hw/intc/arm_gicv3_its: Allow save/restore
Krzysztof Kozlowski (9):
hw/intc/exynos4210_gic: Use more meaningful name for local variable
hw/timer/exynos4210_mct: Fix checkpatch style errors
hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
hw/timer/exynos4210_mct: Remove unused defines
hw/arm/exynos: Move DRAM initialization next boards
hw/arm/exynos: Declare local variables in some order
hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
hw/intc/exynos4210_gic: Constify array of combiner interrupts
hw/misc/exynos4210_pmu: Add support for system poweroff
Pranith Kumar (1):
timer.h: Provide better monotonic time
hw/misc/Makefile.objs | 1 +
include/hw/arm/exynos4210.h | 5 +-
include/hw/intc/arm_gicv3_its_common.h | 8 +
include/migration/vmstate.h | 2 +
include/qemu/timer.h | 5 +-
include/sysemu/kvm.h | 11 +-
hw/arm/aspeed.c | 9 +
hw/arm/exynos4210.c | 27 +--
hw/arm/exynos4_boards.c | 50 +++-
hw/intc/arm_gic_kvm.c | 9 +-
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_its_common.c | 12 +-
hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++--
hw/intc/arm_gicv3_kvm.c | 48 +++-
hw/intc/exynos4210_gic.c | 14 +-
hw/misc/exynos4210_pmu.c | 20 +-
hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++
hw/timer/aspeed_timer.c | 37 ++-
hw/timer/exynos4210_mct.c | 50 ++--
kvm-all.c | 14 +-
default-configs/arm-softmmu.mak | 1 +
21 files changed, 741 insertions(+), 116 deletions(-)
create mode 100644 hw/misc/tmp421.c
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors Peter Maydell
` (17 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
There are to SysBusDevice variables in exynos4210_gic_realize()
function: one for the device itself and second for arm_gic device. Add
a prefix "gic" to the second one so it will be easier to understand the
code.
While at it, put local uninitialized 'i' variable at the end, next to
other uninitialized ones.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/exynos4210_gic.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index 2a55817..62acede 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -286,21 +286,21 @@ static void exynos4210_gic_init(Object *obj)
DeviceState *dev = DEVICE(obj);
Exynos4210GicState *s = EXYNOS4210_GIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- uint32_t i;
const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
const char dist_prefix[] = "exynos4210-gic-alias_dist";
char cpu_alias_name[sizeof(cpu_prefix) + 3];
char dist_alias_name[sizeof(cpu_prefix) + 3];
- SysBusDevice *busdev;
+ SysBusDevice *gicbusdev;
+ uint32_t i;
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
qdev_init_nofail(s->gic);
- busdev = SYS_BUS_DEVICE(s->gic);
+ gicbusdev = SYS_BUS_DEVICE(s->gic);
/* Pass through outbound IRQ lines from the GIC */
- sysbus_pass_irq(sbd, busdev);
+ sysbus_pass_irq(sbd, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
@@ -316,7 +316,7 @@ static void exynos4210_gic_init(Object *obj)
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
memory_region_init_alias(&s->cpu_alias[i], obj,
cpu_alias_name,
- sysbus_mmio_get_region(busdev, 1),
+ sysbus_mmio_get_region(gicbusdev, 1),
0,
EXYNOS4210_GIC_CPU_REGION_SIZE);
memory_region_add_subregion(&s->cpu_container,
@@ -326,7 +326,7 @@ static void exynos4210_gic_init(Object *obj)
sprintf(dist_alias_name, "%s%x", dist_prefix, i);
memory_region_init_alias(&s->dist_alias[i], obj,
dist_alias_name,
- sysbus_mmio_get_region(busdev, 0),
+ sysbus_mmio_get_region(gicbusdev, 0),
0,
EXYNOS4210_GIC_DIST_REGION_SIZE);
memory_region_add_subregion(&s->dist_container,
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines Peter Maydell
` (16 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Fix checkpatch errors:
1. ERROR: spaces required around that '+' (ctx:VxV)
2. ERROR: spaces required around that '&' (ctx:VxV)
No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/exynos4210_mct.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index a2ec392..2404fb7 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -937,7 +937,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
{
uint32_t freq = s->freq;
s->freq = 24000000 /
- ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) *
+ ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) *
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
if (freq != s->freq) {
@@ -1162,7 +1162,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
- if (offset&0x4) {
+ if (offset & 0x4) {
s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
} else {
s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines Peter Maydell
` (15 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Statements under 'case' were in some places wrongly indented bringing
confusion and making the code less readable. Remove also few unneeded
blank lines. No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++-------------------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index 2404fb7..ea5f99d 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -1016,9 +1016,9 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
- index = GET_G_COMP_IDX(offset);
- shift = 8 * (offset & 0x4);
- value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
+ index = GET_G_COMP_IDX(offset);
+ shift = 8 * (offset & 0x4);
+ value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
break;
case G_TCON:
@@ -1067,7 +1067,6 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
lt_i = GET_L_TIMER_IDX(offset);
value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
-
break;
case L0_TCON: case L1_TCON:
@@ -1153,23 +1152,23 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
- index = GET_G_COMP_IDX(offset);
- shift = 8 * (offset & 0x4);
- s->g_timer.reg.comp[index] =
- (s->g_timer.reg.comp[index] &
- (((uint64_t)UINT32_MAX << 32) >> shift)) +
- (value << shift);
+ index = GET_G_COMP_IDX(offset);
+ shift = 8 * (offset & 0x4);
+ s->g_timer.reg.comp[index] =
+ (s->g_timer.reg.comp[index] &
+ (((uint64_t)UINT32_MAX << 32) >> shift)) +
+ (value << shift);
- DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
+ DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
- if (offset & 0x4) {
- s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
- } else {
- s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
- }
+ if (offset & 0x4) {
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
+ } else {
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
+ }
- exynos4210_gfrc_restart(s);
- break;
+ exynos4210_gfrc_restart(s);
+ break;
case G_TCON:
old_val = s->g_timer.reg.tcon;
@@ -1207,7 +1206,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case G_INT_ENB:
-
/* Raise IRQ if transition from disabled to enabled and CSTAT pending */
for (i = 0; i < MCT_GT_CMP_NUM; i++) {
if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
@@ -1288,7 +1286,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case L0_TCNTB: case L1_TCNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
@@ -1316,7 +1313,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case L0_ICNTB: case L1_ICNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
@@ -1353,13 +1349,12 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
if (icntb_max[lt_i] < value) {
icntb_max[lt_i] = value;
}
-DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
- lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
+ DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
+ lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
#endif
-break;
+ break;
case L0_FRCNTB: case L1_FRCNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards Peter Maydell
` (14 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Remove defines not used anywhere.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/exynos4210_mct.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index ea5f99d..e4ef4cf 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -173,13 +173,10 @@ enum LocalTimerRegCntIndexes {
L_REG_CNT_AMOUNT
};
-#define MCT_NIRQ 6
#define MCT_SFR_SIZE 0x444
#define MCT_GT_CMP_NUM 4
-#define MCT_GT_MAX_VAL UINT64_MAX
-
#define MCT_GT_COUNTER_STEP 0x100000000ULL
#define MCT_LT_COUNTER_STEP 0x100000000ULL
#define MCT_LT_CNT_LOW_LIMIT 0x100
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order Peter Maydell
` (13 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization
from exynos4210.c to exynos4_boards.c because DRAM is board specific,
not SoC.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/exynos4210.h | 5 +----
hw/arm/exynos4210.c | 20 +-----------------
hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++-------
3 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index d9e0801..098a69e 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -93,8 +93,6 @@ typedef struct Exynos4210State {
MemoryRegion iram_mem;
MemoryRegion irom_mem;
MemoryRegion irom_alias_mem;
- MemoryRegion dram0_mem;
- MemoryRegion dram1_mem;
MemoryRegion boot_secondary;
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
@@ -103,8 +101,7 @@ typedef struct Exynos4210State {
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
- unsigned long ram_size);
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
/* Initialize exynos4210 IRQ subsystem stub */
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 960f27e..0da877f 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -160,13 +160,11 @@ static uint64_t exynos4210_calc_affinity(int cpu)
return mp_affinity;
}
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
- unsigned long ram_size)
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
int i, n;
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
- unsigned long mem_size;
DeviceState *dev;
SysBusDevice *busdev;
ObjectClass *cpu_oc;
@@ -299,22 +297,6 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
&s->iram_mem);
- /* DRAM */
- mem_size = ram_size;
- if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
- memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
- mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
- vmstate_register_ram_global(&s->dram1_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
- &s->dram1_mem);
- mem_size = EXYNOS4210_DRAM_MAX_SIZE;
- }
- memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
- &error_fatal);
- vmstate_register_ram_global(&s->dram0_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
- &s->dram0_mem);
-
/* PMU.
* The only reason of existence at the moment is that secondary CPU boot
* loader uses PMU INFORM5 register as a holding pen.
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 4853c31..6240b26 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -22,6 +22,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu-common.h"
#include "cpu.h"
@@ -56,6 +57,12 @@ typedef enum Exynos4BoardType {
EXYNOS4_NUM_OF_BOARDS
} Exynos4BoardType;
+typedef struct Exynos4BoardState {
+ Exynos4210State *soc;
+ MemoryRegion dram0_mem;
+ MemoryRegion dram1_mem;
+} Exynos4BoardState;
+
static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
[EXYNOS4_BOARD_NURI] = 0xD33,
[EXYNOS4_BOARD_SMDKC210] = 0xB16,
@@ -96,9 +103,34 @@ static void lan9215_init(uint32_t base, qemu_irq irq)
}
}
-static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
- Exynos4BoardType board_type)
+static void exynos4_boards_init_ram(Exynos4BoardState *s,
+ MemoryRegion *system_mem,
+ unsigned long ram_size)
+{
+ unsigned long mem_size = ram_size;
+
+ if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
+ memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
+ mem_size - EXYNOS4210_DRAM_MAX_SIZE,
+ &error_fatal);
+ vmstate_register_ram_global(&s->dram1_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
+ &s->dram1_mem);
+ mem_size = EXYNOS4210_DRAM_MAX_SIZE;
+ }
+
+ memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
+ &error_fatal);
+ vmstate_register_ram_global(&s->dram0_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
+ &s->dram0_mem);
+}
+
+static Exynos4BoardState *
+exynos4_boards_init_common(MachineState *machine,
+ Exynos4BoardType board_type)
{
+ Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
@@ -127,8 +159,12 @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
machine->kernel_cmdline,
machine->initrd_filename);
- return exynos4210_init(get_system_memory(),
- exynos4_board_ram_size[board_type]);
+ exynos4_boards_init_ram(s, get_system_memory(),
+ exynos4_board_ram_size[board_type]);
+
+ s->soc = exynos4210_init(get_system_memory());
+
+ return s;
}
static void nuri_init(MachineState *machine)
@@ -140,11 +176,11 @@ static void nuri_init(MachineState *machine)
static void smdkc210_init(MachineState *machine)
{
- Exynos4210State *s = exynos4_boards_init_common(machine,
- EXYNOS4_BOARD_SMDKC210);
+ Exynos4BoardState *s = exynos4_boards_init_common(machine,
+ EXYNOS4_BOARD_SMDKC210);
lan9215_init(SMDK_LAN9118_BASE_ADDR,
- qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));
+ qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string Peter Maydell
` (12 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Bring some more readability by declaring local function variables: first
initialized ones and then the rest (with reversed-christmas-tree order).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 0da877f..27a7bf2 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -162,12 +162,12 @@ static uint64_t exynos4210_calc_affinity(int cpu)
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
- int i, n;
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
- DeviceState *dev;
SysBusDevice *busdev;
ObjectClass *cpu_oc;
+ DeviceState *dev;
+ int i, n;
cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
assert(cpu_oc);
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts Peter Maydell
` (11 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
Use a define for a9mpcore_priv device type name instead of hard-coded
string.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 27a7bf2..0050626 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -26,6 +26,7 @@
#include "qemu-common.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "hw/cpu/a9mpcore.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
@@ -211,7 +212,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
}
/* Private memory region and Internal GIC */
- dev = qdev_create(NULL, "a9mpcore_priv");
+ dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff Peter Maydell
` (10 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
The static array of interrupt combiner mappings is not modified so it
can be made const for code safeness.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/exynos4210_gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index 62acede..b6b00a4 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -116,7 +116,7 @@ enum ExtInt {
* which is INTG16 in Internal Interrupt Combiner.
*/
-static uint32_t
+static const uint32_t
combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
/* int combiner groups 16-19 */
{ }, { }, { }, { },
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time Peter Maydell
` (9 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Krzysztof Kozlowski <krzk@kernel.org>
On all Exynos-based boards, the system powers down itself by driving
PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU.
Handle writing to respective PMU register to fix power off failure:
reboot: Power down
Unable to poweroff system
shutdown: 31 output lines suppressed due to ratelimiting
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000
CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14)
[<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c)
[<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268)
[<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4)
[<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0)
[<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c)
Additionally the initial value of PS_HOLD has to be changed because
recent Linux kernel (v4.12-rc1) uses regmap cache for this access.
When the register is kept at reset value, the kernel will not issue a
write to it. Usually the bootloader sets the eight bit of PS_HOLD high
so mimic its existence here.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
index 63a8ccd..0d7b64c 100644
--- a/hw/misc/exynos4210_pmu.c
+++ b/hw/misc/exynos4210_pmu.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
#ifndef DEBUG_PMU
#define DEBUG_PMU 0
@@ -350,7 +351,11 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
{"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
{"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
{"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
- {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200},
+ /*
+ * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit.
+ * DATA bit high, set usually by bootloader, keeps system on.
+ */
+ {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
{"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
{"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
{"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
@@ -397,6 +402,12 @@ typedef struct Exynos4210PmuState {
uint32_t reg[PMU_NUM_OF_REGISTERS];
} Exynos4210PmuState;
+static void exynos4210_pmu_poweroff(void)
+{
+ PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+}
+
static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -428,6 +439,13 @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
(uint32_t)offset, (uint32_t)val);
s->reg[i] = val;
+ if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
+ /*
+ * We are interested only in setting data bit
+ * of PS_HOLD_CONTROL register to indicate power off request.
+ */
+ exynos4210_pmu_poweroff();
+ }
return;
}
reg_p++;
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff Peter Maydell
@ 2017-06-13 14:06 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model Peter Maydell
` (8 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:06 UTC (permalink / raw)
To: qemu-devel
From: Pranith Kumar <bobby.prani@gmail.com>
Tested and confirmed that the stretch i386 debian qcow2 image on a
raspberry pi 2 works.
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20170418191817.10430-1-bobby.prani@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/qemu/timer.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index 8a1eb74..1b518bc 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -1020,10 +1020,9 @@ static inline int64_t cpu_get_host_ticks(void)
/* The host CPU doesn't have an easily accessible cycle counter.
Just return a monotonically increasing value. This will be
totally wrong, but hopefully better than nothing. */
-static inline int64_t cpu_get_host_ticks (void)
+static inline int64_t cpu_get_host_ticks(void)
{
- static int64_t ticks = 0;
- return ticks++;
+ return get_clock();
}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2017-06-13 14:06 ` [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3 Peter Maydell
` (7 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Cédric Le Goater <clg@kaod.org>
Largely inspired by the TMP105 temperature sensor, here is a model for
the TMP42{1,2,3} temperature sensors.
Specs can be found here :
http://www.ti.com/lit/gpn/tmp421
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++
default-configs/arm-softmmu.mak | 1 +
3 files changed, 404 insertions(+)
create mode 100644 hw/misc/tmp421.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c8b4893..2019846 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -1,6 +1,7 @@
common-obj-$(CONFIG_APPLESMC) += applesmc.o
common-obj-$(CONFIG_MAX111X) += max111x.o
common-obj-$(CONFIG_TMP105) += tmp105.o
+common-obj-$(CONFIG_TMP421) += tmp421.o
common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
common-obj-$(CONFIG_SGA) += sga.o
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
new file mode 100644
index 0000000..4a505ab
--- /dev/null
+++ b/hw/misc/tmp421.c
@@ -0,0 +1,402 @@
+/*
+ * Texas Instruments TMP421 temperature sensor.
+ *
+ * Copyright (c) 2016 IBM Corporation.
+ *
+ * Largely inspired by :
+ *
+ * Texas Instruments TMP105 temperature sensor.
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+/* Manufacturer / Device ID's */
+#define TMP421_MANUFACTURER_ID 0x55
+#define TMP421_DEVICE_ID 0x21
+#define TMP422_DEVICE_ID 0x22
+#define TMP423_DEVICE_ID 0x23
+
+typedef struct DeviceInfo {
+ int model;
+ const char *name;
+} DeviceInfo;
+
+static const DeviceInfo devices[] = {
+ { TMP421_DEVICE_ID, "tmp421" },
+ { TMP422_DEVICE_ID, "tmp422" },
+ { TMP423_DEVICE_ID, "tmp423" },
+};
+
+typedef struct TMP421State {
+ /*< private >*/
+ I2CSlave i2c;
+ /*< public >*/
+
+ int16_t temperature[4];
+
+ uint8_t status;
+ uint8_t config[2];
+ uint8_t rate;
+
+ uint8_t len;
+ uint8_t buf[2];
+ uint8_t pointer;
+
+} TMP421State;
+
+typedef struct TMP421Class {
+ I2CSlaveClass parent_class;
+ DeviceInfo *dev;
+} TMP421Class;
+
+#define TYPE_TMP421 "tmp421-generic"
+#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
+
+#define TMP421_CLASS(klass) \
+ OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
+#define TMP421_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
+
+/* the TMP421 registers */
+#define TMP421_STATUS_REG 0x08
+#define TMP421_STATUS_BUSY (1 << 7)
+#define TMP421_CONFIG_REG_1 0x09
+#define TMP421_CONFIG_RANGE (1 << 2)
+#define TMP421_CONFIG_SHUTDOWN (1 << 6)
+#define TMP421_CONFIG_REG_2 0x0A
+#define TMP421_CONFIG_RC (1 << 2)
+#define TMP421_CONFIG_LEN (1 << 3)
+#define TMP421_CONFIG_REN (1 << 4)
+#define TMP421_CONFIG_REN2 (1 << 5)
+#define TMP421_CONFIG_REN3 (1 << 6)
+
+#define TMP421_CONVERSION_RATE_REG 0x0B
+#define TMP421_ONE_SHOT 0x0F
+
+#define TMP421_RESET 0xFC
+#define TMP421_MANUFACTURER_ID_REG 0xFE
+#define TMP421_DEVICE_ID_REG 0xFF
+
+#define TMP421_TEMP_MSB0 0x00
+#define TMP421_TEMP_MSB1 0x01
+#define TMP421_TEMP_MSB2 0x02
+#define TMP421_TEMP_MSB3 0x03
+#define TMP421_TEMP_LSB0 0x10
+#define TMP421_TEMP_LSB1 0x11
+#define TMP421_TEMP_LSB2 0x12
+#define TMP421_TEMP_LSB3 0x13
+
+static const int32_t mins[2] = { -40000, -55000 };
+static const int32_t maxs[2] = { 127000, 150000 };
+
+static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ TMP421State *s = TMP421(obj);
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+ int offset = ext_range * 64 * 256;
+ int64_t value;
+ int tempid;
+
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
+ error_setg(errp, "error reading %s: %m", name);
+ return;
+ }
+
+ if (tempid >= 4 || tempid < 0) {
+ error_setg(errp, "error reading %s", name);
+ return;
+ }
+
+ value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
+
+ visit_type_int(v, name, &value, errp);
+}
+
+/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8
+ * fixed point, so units are 1/256 centigrades. A simple ratio will do.
+ */
+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ TMP421State *s = TMP421(obj);
+ Error *local_err = NULL;
+ int64_t temp;
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+ int offset = ext_range * 64 * 256;
+ int tempid;
+
+ visit_type_int(v, name, &temp, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
+ error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
+ temp / 1000, temp % 1000);
+ return;
+ }
+
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
+ error_setg(errp, "error reading %s: %m", name);
+ return;
+ }
+
+ if (tempid >= 4 || tempid < 0) {
+ error_setg(errp, "error reading %s", name);
+ return;
+ }
+
+ s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
+}
+
+static void tmp421_read(TMP421State *s)
+{
+ TMP421Class *sc = TMP421_GET_CLASS(s);
+
+ s->len = 0;
+
+ switch (s->pointer) {
+ case TMP421_MANUFACTURER_ID_REG:
+ s->buf[s->len++] = TMP421_MANUFACTURER_ID;
+ break;
+ case TMP421_DEVICE_ID_REG:
+ s->buf[s->len++] = sc->dev->model;
+ break;
+ case TMP421_CONFIG_REG_1:
+ s->buf[s->len++] = s->config[0];
+ break;
+ case TMP421_CONFIG_REG_2:
+ s->buf[s->len++] = s->config[1];
+ break;
+ case TMP421_CONVERSION_RATE_REG:
+ s->buf[s->len++] = s->rate;
+ break;
+ case TMP421_STATUS_REG:
+ s->buf[s->len++] = s->status;
+ break;
+
+ /* FIXME: check for channel enablement in config registers */
+ case TMP421_TEMP_MSB0:
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB1:
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB2:
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_MSB3:
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB0:
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB1:
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB2:
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+ break;
+ case TMP421_TEMP_LSB3:
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+ break;
+ }
+}
+
+static void tmp421_reset(I2CSlave *i2c);
+
+static void tmp421_write(TMP421State *s)
+{
+ switch (s->pointer) {
+ case TMP421_CONVERSION_RATE_REG:
+ s->rate = s->buf[0];
+ break;
+ case TMP421_CONFIG_REG_1:
+ s->config[0] = s->buf[0];
+ break;
+ case TMP421_CONFIG_REG_2:
+ s->config[1] = s->buf[0];
+ break;
+ case TMP421_RESET:
+ tmp421_reset(I2C_SLAVE(s));
+ break;
+ }
+}
+
+static int tmp421_rx(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (s->len < 2) {
+ return s->buf[s->len++];
+ } else {
+ return 0xff;
+ }
+}
+
+static int tmp421_tx(I2CSlave *i2c, uint8_t data)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (s->len == 0) {
+ /* first byte is the register pointer for a read or write
+ * operation */
+ s->pointer = data;
+ s->len++;
+ } else if (s->len == 1) {
+ /* second byte is the data to write. The device only supports
+ * one byte writes */
+ s->buf[0] = data;
+ tmp421_write(s);
+ }
+
+ return 0;
+}
+
+static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
+{
+ TMP421State *s = TMP421(i2c);
+
+ if (event == I2C_START_RECV) {
+ tmp421_read(s);
+ }
+
+ s->len = 0;
+ return 0;
+}
+
+static const VMStateDescription vmstate_tmp421 = {
+ .name = "TMP421",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(len, TMP421State),
+ VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
+ VMSTATE_UINT8(pointer, TMP421State),
+ VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
+ VMSTATE_UINT8(status, TMP421State),
+ VMSTATE_UINT8(rate, TMP421State),
+ VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
+ VMSTATE_I2C_SLAVE(i2c, TMP421State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void tmp421_reset(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+ TMP421Class *sc = TMP421_GET_CLASS(s);
+
+ memset(s->temperature, 0, sizeof(s->temperature));
+ s->pointer = 0;
+
+ s->config[0] = 0; /* TMP421_CONFIG_RANGE */
+
+ /* resistance correction and channel enablement */
+ switch (sc->dev->model) {
+ case TMP421_DEVICE_ID:
+ s->config[1] = 0x1c;
+ break;
+ case TMP422_DEVICE_ID:
+ s->config[1] = 0x3c;
+ break;
+ case TMP423_DEVICE_ID:
+ s->config[1] = 0x7c;
+ break;
+ }
+
+ s->rate = 0x7; /* 8Hz */
+ s->status = 0;
+}
+
+static int tmp421_init(I2CSlave *i2c)
+{
+ TMP421State *s = TMP421(i2c);
+
+ tmp421_reset(&s->i2c);
+
+ return 0;
+}
+
+static void tmp421_initfn(Object *obj)
+{
+ object_property_add(obj, "temperature0", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature1", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature2", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+ object_property_add(obj, "temperature3", "int",
+ tmp421_get_temperature,
+ tmp421_set_temperature, NULL, NULL, NULL);
+}
+
+static void tmp421_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+ TMP421Class *sc = TMP421_CLASS(klass);
+
+ k->init = tmp421_init;
+ k->event = tmp421_event;
+ k->recv = tmp421_rx;
+ k->send = tmp421_tx;
+ dc->vmsd = &vmstate_tmp421;
+ sc->dev = (DeviceInfo *) data;
+}
+
+static const TypeInfo tmp421_info = {
+ .name = TYPE_TMP421,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(TMP421State),
+ .class_size = sizeof(TMP421Class),
+ .instance_init = tmp421_initfn,
+ .abstract = true,
+};
+
+static void tmp421_register_types(void)
+{
+ int i;
+
+ type_register_static(&tmp421_info);
+ for (i = 0; i < ARRAY_SIZE(devices); ++i) {
+ TypeInfo ti = {
+ .name = devices[i].name,
+ .parent = TYPE_TMP421,
+ .class_init = tmp421_class_init,
+ .class_data = (void *) &devices[i],
+ };
+ type_register(&ti);
+ }
+}
+
+type_init(tmp421_register_types)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 78d7af0..93e995d 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -15,6 +15,7 @@ CONFIG_TWL92230=y
CONFIG_TSC2005=y
CONFIG_LM832X=y
CONFIG_TMP105=y
+CONFIG_TMP421=y
CONFIG_STELLARIS=y
CONFIG_STELLARIS_INPUT=y
CONFIG_STELLARIS_ENET=y
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set Peter Maydell
` (6 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Cédric Le Goater <clg@kaod.org>
Temperatures can be changed from the monitor with :
(qemu) qom-set /machine/unattached/device[2] temperature0 12000
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e824ea8..155eeb2 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -239,10 +239,19 @@ static void aspeed_board_init(MachineState *machine,
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
+ DeviceState *dev;
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
* enough to provide basic RTC features. Alarms will be missing */
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
+
+ /* add a TMP423 temperature sensor */
+ dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
+ "tmp423", 0x4c);
+ object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
+ object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
+ object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
+ object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
}
static void palmetto_bmc_init(MachineState *machine)
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3 Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access Peter Maydell
` (5 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Cédric Le Goater <clg@kaod.org>
When a timer is enabled before a reload value is set, the controller
waits for a reload value to be set before starting decrementing. This
fix tries to cover that case by changing the timer expiry only when
a reload value is valid.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++--------
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 9b70ee0..50acbf5 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -130,15 +130,26 @@ static uint64_t calculate_next(struct AspeedTimer *t)
next = seq[1];
} else if (now < seq[2]) {
next = seq[2];
- } else {
+ } else if (t->reload) {
reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
t->start = now - ((now - t->start) % reload_ns);
+ } else {
+ /* no reload value, return 0 */
+ break;
}
}
return next;
}
+static void aspeed_timer_mod(AspeedTimer *t)
+{
+ uint64_t next = calculate_next(t);
+ if (next) {
+ timer_mod(&t->timer, next);
+ }
+}
+
static void aspeed_timer_expire(void *opaque)
{
AspeedTimer *t = opaque;
@@ -164,7 +175,7 @@ static void aspeed_timer_expire(void *opaque)
qemu_set_irq(t->irq, t->level);
}
- timer_mod(&t->timer, calculate_next(t));
+ aspeed_timer_mod(t);
}
static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
@@ -227,10 +238,23 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
uint32_t value)
{
AspeedTimer *t;
+ uint32_t old_reload;
trace_aspeed_timer_set_value(timer, reg, value);
t = &s->timers[timer];
switch (reg) {
+ case TIMER_REG_RELOAD:
+ old_reload = t->reload;
+ t->reload = value;
+
+ /* If the reload value was not previously set, or zero, and
+ * the current value is valid, try to start the timer if it is
+ * enabled.
+ */
+ if (old_reload || !t->reload) {
+ break;
+ }
+
case TIMER_REG_STATUS:
if (timer_enabled(t)) {
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -238,17 +262,14 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
uint32_t rate = calculate_rate(t);
t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
- timer_mod(&t->timer, calculate_next(t));
+ aspeed_timer_mod(t);
}
break;
- case TIMER_REG_RELOAD:
- t->reload = value;
- break;
case TIMER_REG_MATCH_FIRST:
case TIMER_REG_MATCH_SECOND:
t->match[reg - 2] = value;
if (timer_enabled(t)) {
- timer_mod(&t->timer, calculate_next(t));
+ aspeed_timer_mod(t);
}
break;
default:
@@ -268,7 +289,7 @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable)
trace_aspeed_timer_ctrl_enable(t->id, enable);
if (enable) {
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- timer_mod(&t->timer, calculate_next(t));
+ aspeed_timer_mod(t);
} else {
timer_del(&t->timer);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore Peter Maydell
` (4 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
In some circumstances, we don't want to abort if the
kvm_device_access fails. This will be the case during ITS
migration, in case the ITS table save/restore fails because
the guest did not program the vITS correctly. So let's pass an
error object to the function and return the ioctl value. New
callers will be able to make a decision upon this returned
value.
Existing callers pass &error_abort which will cause the
function to abort on failure.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com
[PMM: wrapped long line]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/sysemu/kvm.h | 11 +++++++----
hw/intc/arm_gic_kvm.c | 9 +++++----
hw/intc/arm_gicv3_its_kvm.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 14 +++++++-------
kvm-all.c | 14 ++++++++------
5 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index a45c145..1e91613 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -294,12 +294,15 @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr);
* @attr: the attribute of that group to set or get
* @val: pointer to a storage area for the value
* @write: true for set and false for get operation
+ * @errp: error object handle
*
- * This function is not allowed to fail. Use kvm_device_check_attr()
- * in order to check for the availability of optional attributes.
+ * Returns: 0 on success
+ * < 0 on error
+ * Use kvm_device_check_attr() in order to check for the availability
+ * of optional attributes.
*/
-void kvm_device_access(int fd, int group, uint64_t attr,
- void *val, bool write);
+int kvm_device_access(int fd, int group, uint64_t attr,
+ void *val, bool write, Error **errp);
/**
* kvm_create_device - create a KVM device for the device control API
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index af5cd36..ae095d0 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -100,14 +100,14 @@ static void kvm_gicd_access(GICState *s, int offset, int cpu,
uint32_t *val, bool write)
{
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
- KVM_VGIC_ATTR(offset, cpu), val, write);
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
}
static void kvm_gicc_access(GICState *s, int offset, int cpu,
uint32_t *val, bool write)
{
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
- KVM_VGIC_ATTR(offset, cpu), val, write);
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
}
#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
@@ -538,13 +538,14 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
uint32_t numirqs = s->num_irq;
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
- &numirqs, true);
+ &numirqs, true, &error_abort);
}
/* Tell the kernel to complete VGIC initialization now */
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
KVM_DEV_ARM_VGIC_CTRL_INIT)) {
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
+ &error_abort);
}
} else if (ret != -ENODEV && ret != -ENOTSUP) {
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index a0441d6..340c2b0 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -78,7 +78,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
/* explicit init of the ITS */
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
/* register the base address */
kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 4ee2baa..b70ee27 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -93,7 +93,7 @@ static inline void kvm_gicd_access(GICv3State *s, int offset,
{
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
KVM_VGIC_ATTR(offset, 0),
- val, write);
+ val, write, &error_abort);
}
static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
@@ -101,7 +101,7 @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
{
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
- val, write);
+ val, write, &error_abort);
}
static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
@@ -109,7 +109,7 @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
{
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
- val, write);
+ val, write, &error_abort);
}
static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
@@ -119,7 +119,7 @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
(VGIC_LEVEL_INFO_LINE_LEVEL <<
KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
- val, write);
+ val, write, &error_abort);
}
/* Loop through each distributor IRQ related register; since bits
@@ -630,7 +630,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
/* Initialize to actual HW supported configuration */
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
- &c->icc_ctlr_el1[GICV3_NS], false);
+ &c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
}
@@ -717,11 +717,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
}
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
- 0, &s->num_irq, true);
+ 0, &s->num_irq, true, &error_abort);
/* Tell the kernel to complete VGIC initialization now */
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd);
diff --git a/kvm-all.c b/kvm-all.c
index 44b3cf4..ab8262f 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -23,6 +23,7 @@
#include "qemu/option.h"
#include "qemu/config-file.h"
#include "qemu/error-report.h"
+#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/pci/msi.h"
#include "hw/pci/msix.h"
@@ -2216,8 +2217,8 @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr)
return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1;
}
-void kvm_device_access(int fd, int group, uint64_t attr,
- void *val, bool write)
+int kvm_device_access(int fd, int group, uint64_t attr,
+ void *val, bool write, Error **errp)
{
struct kvm_device_attr kvmattr;
int err;
@@ -2231,11 +2232,12 @@ void kvm_device_access(int fd, int group, uint64_t attr,
write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR,
&kvmattr);
if (err < 0) {
- error_report("KVM_%s_DEVICE_ATTR failed: %s",
- write ? "SET" : "GET", strerror(-err));
- error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr);
- abort();
+ error_setg_errno(errp, -err,
+ "KVM_%s_DEVICE_ATTR failed: Group %d "
+ "attr 0x%016" PRIx64,
+ write ? "SET" : "GET", group, attr);
}
+ return err;
}
/* Return 1 on success, 0 on failure */
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save Peter Maydell
` (3 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
We need to handle both registers and ITS tables. While
register handling is standard, ITS table handling is more
challenging since the kernel API is devised so that the
tables are flushed into guest RAM and not in vmstate buffers.
Flushing the ITS tables on device pre_save() is too late
since the guest RAM is already saved at this point.
Table flushing needs to happen when we are sure the vcpus
are stopped and before the last dirty page saving. The
right point is RUN_STATE_FINISH_MIGRATE but sometimes the
VM gets stopped before migration launch so let's simply
flush the tables each time the VM gets stopped.
For regular ITS registers we just can use vmstate pre_save()
and post_load() callbacks.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/arm_gicv3_its_common.h | 8 +++
hw/intc/arm_gicv3_its_common.c | 10 ++++
hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++
3 files changed, 123 insertions(+)
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
index 1ba1894..fd1fe64 100644
--- a/include/hw/intc/arm_gicv3_its_common.h
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -28,6 +28,13 @@
#define ITS_TRANS_SIZE 0x10000
#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
+#define GITS_CTLR 0x0
+#define GITS_IIDR 0x4
+#define GITS_CBASER 0x80
+#define GITS_CWRITER 0x88
+#define GITS_CREADR 0x90
+#define GITS_BASER 0x100
+
struct GICv3ITSState {
SysBusDevice parent_obj;
@@ -43,6 +50,7 @@ struct GICv3ITSState {
/* Registers */
uint32_t ctlr;
+ uint32_t iidr;
uint64_t cbaser;
uint64_t cwriter;
uint64_t creadr;
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index 9d67c5c..696c11c 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -49,6 +49,15 @@ static const VMStateDescription vmstate_its = {
.pre_save = gicv3_its_pre_save,
.post_load = gicv3_its_post_load,
.unmigratable = true,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(ctlr, GICv3ITSState),
+ VMSTATE_UINT32(iidr, GICv3ITSState),
+ VMSTATE_UINT64(cbaser, GICv3ITSState),
+ VMSTATE_UINT64(cwriter, GICv3ITSState),
+ VMSTATE_UINT64(creadr, GICv3ITSState),
+ VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
+ VMSTATE_END_OF_LIST()
+ },
};
static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
@@ -118,6 +127,7 @@ static void gicv3_its_common_reset(DeviceState *dev)
s->cbaser = 0;
s->cwriter = 0;
s->creadr = 0;
+ s->iidr = 0;
memset(&s->baser, 0, sizeof(s->baser));
gicv3_its_post_load(s, 0);
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 340c2b0..4cd8f5f 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -53,6 +53,33 @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
}
+/**
+ * vm_change_state_handler - VM change state callback aiming at flushing
+ * ITS tables into guest RAM
+ *
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
+ */
+static void vm_change_state_handler(void *opaque, int running,
+ RunState state)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ Error *err = NULL;
+ int ret;
+
+ if (running) {
+ return;
+ }
+
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
+ if (err) {
+ error_report_err(err);
+ }
+ if (ret < 0 && ret != -EFAULT) {
+ abort();
+ }
+}
+
static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
@@ -89,6 +116,8 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
kvm_msi_use_devid = true;
kvm_gsi_direct_mapping = false;
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
+
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
}
static void kvm_arm_its_init(Object *obj)
@@ -102,6 +131,80 @@ static void kvm_arm_its_init(Object *obj)
&error_abort);
}
+/**
+ * kvm_arm_its_pre_save - handles the saving of ITS registers.
+ * ITS tables are flushed into guest RAM separately and earlier,
+ * through the VM change state handler, since at the moment pre_save()
+ * is called, the guest RAM has already been saved.
+ */
+static void kvm_arm_its_pre_save(GICv3ITSState *s)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_BASER + i * 8, &s->baser[i], false,
+ &error_abort);
+ }
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CTLR, &s->ctlr, false, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CBASER, &s->cbaser, false, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CREADR, &s->creadr, false, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CWRITER, &s->cwriter, false, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_IIDR, &s->iidr, false, &error_abort);
+}
+
+/**
+ * kvm_arm_its_post_load - Restore both the ITS registers and tables
+ */
+static void kvm_arm_its_post_load(GICv3ITSState *s)
+{
+ int i;
+
+ if (!s->iidr) {
+ return;
+ }
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_IIDR, &s->iidr, true, &error_abort);
+
+ /*
+ * must be written before GITS_CREADR since GITS_CBASER write
+ * access resets GITS_CREADR.
+ */
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CBASER, &s->cbaser, true, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CREADR, &s->creadr, true, &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CWRITER, &s->cwriter, true, &error_abort);
+
+
+ for (i = 0; i < 8; i++) {
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_BASER + i * 8, &s->baser[i], true,
+ &error_abort);
+ }
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
+ &error_abort);
+
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CTLR, &s->ctlr, true, &error_abort);
+}
+
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -109,6 +212,8 @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
dc->realize = kvm_arm_its_realize;
icc->send_msi = kvm_its_send_msi;
+ icc->pre_save = kvm_arm_its_pre_save;
+ icc->post_load = kvm_arm_its_post_load;
}
static const TypeInfo kvm_arm_its_info = {
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore Peter Maydell
` (2 subsequent siblings)
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
This patch adds the flush of the LPI pending bits into the
redistributor pending tables. This happens on VM stop.
There is no explicit restore as the tables are implicitly sync'ed
on ITS table restore and on LPI enable at redistributor level.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index b70ee27..6051c77 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -25,6 +25,7 @@
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "sysemu/sysemu.h"
#include "kvm_arm.h"
#include "gicv3_internal.h"
#include "vgic_common.h"
@@ -680,6 +681,35 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
REGINFO_SENTINEL
};
+/**
+ * vm_change_state_handler - VM change state callback aiming at flushing
+ * RDIST pending tables into guest RAM
+ *
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
+ */
+static void vm_change_state_handler(void *opaque, int running,
+ RunState state)
+{
+ GICv3State *s = (GICv3State *)opaque;
+ Error *err = NULL;
+ int ret;
+
+ if (running) {
+ return;
+ }
+
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES,
+ NULL, true, &err);
+ if (err) {
+ error_report_err(err);
+ }
+ if (ret < 0 && ret != -EFAULT) {
+ abort();
+ }
+}
+
+
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
{
GICv3State *s = KVM_ARM_GICV3(dev);
@@ -751,6 +781,10 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
return;
}
}
+ if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
+ }
}
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save Peter Maydell
@ 2017-06-13 14:07 ` Peter Maydell
2017-06-13 14:51 ` [Qemu-devel] [PULL 00/17] target-arm queue no-reply
2017-06-13 17:17 ` Peter Maydell
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 14:07 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
We change the restoration priority of both the GICv3 and ITS. The
GICv3 must be restored before the ITS and the ITS needs to be restored
before PCIe devices since it translates their MSI transactions.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/migration/vmstate.h | 2 ++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_its_common.c | 2 +-
hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------
4 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 79a4b35..f3f3c2a 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -149,6 +149,8 @@ enum VMStateFlags {
typedef enum {
MIG_PRI_DEFAULT = 0,
MIG_PRI_IOMMU, /* Must happen before PCI devices */
+ MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */
+ MIG_PRI_GICV3, /* Must happen before the ITS */
MIG_PRI_MAX,
} MigrationPriority;
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index c6493d6..4228b7c 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -145,6 +145,7 @@ static const VMStateDescription vmstate_gicv3 = {
.minimum_version_id = 1,
.pre_save = gicv3_pre_save,
.post_load = gicv3_post_load,
+ .priority = MIG_PRI_GICV3,
.fields = (VMStateField[]) {
VMSTATE_UINT32(gicd_ctlr, GICv3State),
VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index 696c11c..68b20fc 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -48,7 +48,7 @@ static const VMStateDescription vmstate_its = {
.name = "arm_gicv3_its",
.pre_save = gicv3_its_pre_save,
.post_load = gicv3_its_post_load,
- .unmigratable = true,
+ .priority = MIG_PRI_GICV3_ITS,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctlr, GICv3ITSState),
VMSTATE_UINT32(iidr, GICv3ITSState),
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 4cd8f5f..1f8991b 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -85,18 +85,6 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
Error *local_err = NULL;
- /*
- * Block migration of a KVM GICv3 ITS device: the API for saving and
- * restoring the state in the kernel is not yet available
- */
- error_setg(&s->migration_blocker, "vITS migration is not implemented");
- migrate_add_blocker(s->migration_blocker, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- error_free(s->migration_blocker);
- return;
- }
-
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
if (s->dev_fd < 0) {
error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
@@ -113,6 +101,18 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
gicv3_its_init_mmio(s, NULL);
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+ GITS_CTLR)) {
+ error_setg(&s->migration_blocker, "This operating system kernel "
+ "does not support vITS migration");
+ migrate_add_blocker(s->migration_blocker, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ error_free(s->migration_blocker);
+ return;
+ }
+ }
+
kvm_msi_use_devid = true;
kvm_gsi_direct_mapping = false;
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2017-06-13 14:07 ` [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore Peter Maydell
@ 2017-06-13 14:51 ` no-reply
2017-06-13 17:17 ` Peter Maydell
18 siblings, 0 replies; 30+ messages in thread
From: no-reply @ 2017-06-13 14:51 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Message-id: 1497362826-21125-1-git-send-email-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/17] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-quick@centos6
time make docker-test-mingw@fedora
time make docker-test-build@min-glib
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1497362826-21125-1-git-send-email-peter.maydell@linaro.org -> patchew/1497362826-21125-1-git-send-email-peter.maydell@linaro.org
* [new tag] patchew/20170613140546.28227-1-vadim.galitsyn@profitbricks.com -> patchew/20170613140546.28227-1-vadim.galitsyn@profitbricks.com
Switched to a new branch 'test'
e8a726b hw/intc/arm_gicv3_its: Allow save/restore
9f1cade hw/intc/arm_gicv3_kvm: Implement pending table save
8ea3d4b hw/intc/arm_gicv3_its: Implement state save/restore
6dfdedf kvm-all: Pass an error object to kvm_device_access
e9f64e5 timer/aspeed: fix timer enablement when a reload is not set
2749fa4 aspeed: add a temp sensor device on I2C bus 3
9dec9b2 hw/misc: add a TMP42{1, 2, 3} device model
4aa7d8e timer.h: Provide better monotonic time
f00c5e5 hw/misc/exynos4210_pmu: Add support for system poweroff
cbe3c64 hw/intc/exynos4210_gic: Constify array of combiner interrupts
fe2b380 hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
cef2b8f hw/arm/exynos: Declare local variables in some order
162dc61 hw/arm/exynos: Move DRAM initialization next boards
9f45c51 hw/timer/exynos4210_mct: Remove unused defines
5d39e71 hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
55dfae7 hw/timer/exynos4210_mct: Fix checkpatch style errors
f9be1bb hw/intc/exynos4210_gic: Use more meaningful name for local variable
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-bn1jp38n/src/dtc'...
Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
BUILD centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-bn1jp38n/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
ccache-3.1.6-2.el6.x86_64
epel-release-6-8.noarch
gcc-4.4.7-17.el6.x86_64
git-1.7.1-4.el6_7.1.x86_64
glib2-devel-2.28.8-5.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
make-3.81-23.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
tar-1.23-15.el6_8.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release
HOSTNAME=f52622090151
TERM=xterm
MAKEFLAGS= -j8
HISTSIZE=1000
J=8
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
LANG=en_US.UTF-8
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES= dtc
DEBUG=
G_BROKEN_FILENAMES=1
CCACHE_HASHDIR=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install
/tmp/qemu-test/src/configure: line 4683: c++: command not found
No C++ compiler available; disabling C++ specific optional code
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install/share/qemu
binary directory /var/tmp/qemu-build/install/bin
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib/qemu
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install/etc
local state directory /var/tmp/qemu-build/install/var
Manual directory /var/tmp/qemu-build/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled no
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
pixman system
SDL support yes (1.2.14)
GTK support no
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support no
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support no
VNC PNG support no
xen support no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
RDMA support no
TCG interpreter no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
QOM debugging yes
Live block migration yes
lzo support no
snappy support no
bzip2 support no
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN aarch64-softmmu/config-devices.mak.tmp
GEN x86_64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN qapi-types.c
GEN aarch64-softmmu/config-devices.mak
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN backends/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN backends/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
CHK version_gen.h
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
UPD version_gen.h
make[1]: bison: Command not found
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/util.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
make[1]: flex: Command not found
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
make[1]: flex: Command not found
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
LEX convert-dtsv0-lexer.lex.c
LEX dtc-lexer.lex.c
make[1]: flex: Command not found
make[1]: flex: Command not found
BISON dtc-parser.tab.c
make[1]: bison: Command not found
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qmp-marshal.c
GEN qga/qapi-generated/qga-qapi-visit.h
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qdict.o
CC qobject/qstring.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/aio-posix.o
CC util/iohandler.o
CC util/compatfd.o
CC util/mmap-alloc.o
CC util/event_notifier-posix.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/fifo8.o
CC util/hbitmap.o
CC util/acl.o
CC util/error.o
CC util/id.o
CC util/qemu-config.o
CC util/qemu-error.o
CC util/iov.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/systemd.o
CC util/range.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC backends/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/scsi/trace.o
CC hw/usb/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sd/trace.o
CC hw/sparc/trace.o
CC hw/mem/trace.o
CC hw/isa/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/cpu-get-clock.o
CC stubs/clock-warp.o
CC stubs/dump.o
CC stubs/cpu-get-icount.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/migr-blocker.o
CC stubs/machine-init-done.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/vmstate.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC block.o
CC qemu-nbd.o
CC blockjob.o
CC replication.o
CC qemu-io-cmds.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qed.o
CC block/qed-gencb.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-log.o
CC block/vhdx-endian.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-glib.o
CC crypto/hmac.o
CC crypto/aes.o
CC crypto/hmac-glib.o
CC crypto/cipher.o
CC crypto/desrfb.o
CC crypto/tlscredsanon.o
CC crypto/tlscreds.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/random-platform.o
CC crypto/secret.o
CC crypto/pbkdf.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC accel.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC disas/arm.o
CC disas/i386.o
CC fsdev/qemu-fsdev-dummy.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-throttle.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/gus.o
CC hw/audio/adlib.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/m25p80.o
CC hw/block/fdc.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/framebuffer.o
CC hw/display/exynos4210_fimd.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/lm832x.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
In file included from /tmp/qemu-test/src/hw/net/vmxnet3.c:30:
/tmp/qemu-test/src/include/migration/register.h:18: error: redefinition of typedef ‘LoadStateHandler’
/tmp/qemu-test/src/include/migration/vmstate.h:32: note: previous declaration of ‘LoadStateHandler’ was here
make: *** [hw/net/vmxnet3.o] Error 1
make: *** Waiting for unfinished jobs....
tests/docker/Makefile.include:118: recipe for target 'docker-run' failed
make[1]: *** [docker-run] Error 2
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-bn1jp38n/src'
tests/docker/Makefile.include:149: recipe for target 'docker-run-test-quick@centos6' failed
make: *** [docker-run-test-quick@centos6] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2017-06-13 14:51 ` [Qemu-devel] [PULL 00/17] target-arm queue no-reply
@ 2017-06-13 17:17 ` Peter Maydell
18 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2017-06-13 17:17 UTC (permalink / raw)
To: QEMU Developers
On 13 June 2017 at 15:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> Target-arm queue...
>
> thanks
> -- PMM
>
> The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4:
>
> Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613
>
> for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5:
>
> hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * vITS: Support save/restore
> * timer/aspeed: Fix timer enablement when reload is not set
> * aspped: add temperature sensor device
> * timer.h: Provide better monotonic time on ARM hosts
> * exynos4210: various cleanups
> * exynos4210: support system poweroff
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PULL 00/17] target-arm queue
@ 2018-10-16 16:42 Peter Maydell
2018-10-16 17:16 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2018-10-16 16:42 UTC (permalink / raw)
To: qemu-devel
v2: dropped a couple of cadence_gem changes to ID regs that
caused new clang sanitizer warnings.
-- PMM
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
* target/arm: Fix aarch64_sve_change_el wrt EL0
* target/arm: Define fields of ISAR registers
* target/arm: Align cortex-r5 id_isar0
* target/arm: Fix cortex-a7 id_isar0
* net/cadence_gem: Fix various bugs, add support for new
features that will be used by the Xilinx Versal board
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
* target/arm: Add the Cortex-A72
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
* target/arm: Mask PMOVSR writes based on supported counters
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
----------------------------------------------------------------
Aaron Lindsay (2):
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
target/arm: Mask PMOVSR writes based on supported counters
Edgar E. Iglesias (8):
net: cadence_gem: Disable TSU feature bit
net: cadence_gem: Use uint32_t for 32bit descriptor words
net: cadence_gem: Add macro with max number of descriptor words
net: cadence_gem: Add support for extended descriptors
net: cadence_gem: Add support for selecting the DMA MemoryRegion
net: cadence_gem: Implement support for 64bit descriptor addresses
target-arm: powerctl: Enable HVC when starting CPUs to EL2
target/arm: Add the Cortex-A72
Jerome Forissier (1):
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
Peter Maydell (2):
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
Richard Henderson (4):
target/arm: Fix aarch64_sve_change_el wrt EL0
target/arm: Define fields of ISAR registers
target/arm: Align cortex-r5 id_isar0
target/arm: Fix cortex-a7 id_isar0
include/hw/net/cadence_gem.h | 7 +-
target/arm/cpu.h | 95 ++++++++++++++-
hw/arm/virt.c | 4 +
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
target/arm/arm-powerctl.c | 10 ++
target/arm/cpu.c | 7 +-
target/arm/cpu64.c | 66 +++++++++-
target/arm/helper.c | 27 +++--
target/arm/op_helper.c | 6 +-
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
10 files changed, 402 insertions(+), 70 deletions(-)
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PULL 00/17] target-arm queue
2018-10-16 16:42 Peter Maydell
@ 2018-10-16 17:16 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-10-16 17:16 UTC (permalink / raw)
To: QEMU Developers
On 16 October 2018 at 17:42, Peter Maydell <peter.maydell@linaro.org> wrote:
> v2: dropped a couple of cadence_gem changes to ID regs that
> caused new clang sanitizer warnings.
>
> -- PMM
>
> The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
>
> Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
>
> for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
>
> coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
> * target/arm: Fix aarch64_sve_change_el wrt EL0
> * target/arm: Define fields of ISAR registers
> * target/arm: Align cortex-r5 id_isar0
> * target/arm: Fix cortex-a7 id_isar0
> * net/cadence_gem: Fix various bugs, add support for new
> features that will be used by the Xilinx Versal board
> * target-arm: powerctl: Enable HVC when starting CPUs to EL2
> * target/arm: Add the Cortex-A72
> * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
> * target/arm: Mask PMOVSR writes based on supported counters
> * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
> * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2018-10-16 17:17 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3 Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore Peter Maydell
2017-06-13 14:51 ` [Qemu-devel] [PULL 00/17] target-arm queue no-reply
2017-06-13 17:17 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-10-16 16:42 Peter Maydell
2018-10-16 17:16 ` Peter Maydell
2016-03-30 14:57 Peter Maydell
2016-03-30 16:25 ` Peter Maydell
2016-02-03 18:59 Peter Maydell
2016-02-04 12:50 ` Peter Maydell
2015-04-27 15:20 Peter Maydell
2015-04-28 10:33 ` Peter Maydell
2014-05-13 15:31 Peter Maydell
2014-05-15 16:07 ` Peter Maydell
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