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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
Date: Tue, 13 Jun 2017 15:06:52 +0100	[thread overview]
Message-ID: <1497362826-21125-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org>

From: Krzysztof Kozlowski <krzk@kernel.org>

Statements under 'case' were in some places wrongly indented bringing
confusion and making the code less readable.  Remove also few unneeded
blank lines.  No functional changes.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++-------------------------
 1 file changed, 20 insertions(+), 25 deletions(-)

diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index 2404fb7..ea5f99d 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -1016,9 +1016,9 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
 
     case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
     case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
-    index = GET_G_COMP_IDX(offset);
-    shift = 8 * (offset & 0x4);
-    value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
+        index = GET_G_COMP_IDX(offset);
+        shift = 8 * (offset & 0x4);
+        value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
     break;
 
     case G_TCON:
@@ -1067,7 +1067,6 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
         lt_i = GET_L_TIMER_IDX(offset);
 
         value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
-
         break;
 
     case L0_TCON: case L1_TCON:
@@ -1153,23 +1152,23 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
 
     case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
     case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
-    index = GET_G_COMP_IDX(offset);
-    shift = 8 * (offset & 0x4);
-    s->g_timer.reg.comp[index] =
-            (s->g_timer.reg.comp[index] &
-            (((uint64_t)UINT32_MAX << 32) >> shift)) +
-            (value << shift);
+        index = GET_G_COMP_IDX(offset);
+        shift = 8 * (offset & 0x4);
+        s->g_timer.reg.comp[index] =
+                (s->g_timer.reg.comp[index] &
+                (((uint64_t)UINT32_MAX << 32) >> shift)) +
+                (value << shift);
 
-    DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
+        DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
 
-    if (offset & 0x4) {
-        s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
-    } else {
-        s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
-    }
+        if (offset & 0x4) {
+            s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
+        } else {
+            s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
+        }
 
-    exynos4210_gfrc_restart(s);
-    break;
+        exynos4210_gfrc_restart(s);
+        break;
 
     case G_TCON:
         old_val = s->g_timer.reg.tcon;
@@ -1207,7 +1206,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
         break;
 
     case G_INT_ENB:
-
         /* Raise IRQ if transition from disabled to enabled and CSTAT pending */
         for (i = 0; i < MCT_GT_CMP_NUM; i++) {
             if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
@@ -1288,7 +1286,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
         break;
 
     case L0_TCNTB: case L1_TCNTB:
-
         lt_i = GET_L_TIMER_IDX(offset);
         index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
 
@@ -1316,7 +1313,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
         break;
 
     case L0_ICNTB: case L1_ICNTB:
-
         lt_i = GET_L_TIMER_IDX(offset);
         index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
 
@@ -1353,13 +1349,12 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
         if (icntb_max[lt_i] < value) {
             icntb_max[lt_i] = value;
         }
-DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
-        lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
+        DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
+                lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
 #endif
-break;
+        break;
 
     case L0_FRCNTB: case L1_FRCNTB:
-
         lt_i = GET_L_TIMER_IDX(offset);
         index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
 
-- 
2.7.4

  parent reply	other threads:[~2017-06-13 14:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-13 14:06 [Qemu-devel] [PULL 00/17] target-arm queue Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors Peter Maydell
2017-06-13 14:06 ` Peter Maydell [this message]
2017-06-13 14:06 ` [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff Peter Maydell
2017-06-13 14:06 ` [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3 Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save Peter Maydell
2017-06-13 14:07 ` [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore Peter Maydell
2017-06-13 14:51 ` [Qemu-devel] [PULL 00/17] target-arm queue no-reply
2017-06-13 17:17 ` Peter Maydell

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