[Qemu-devel] [PATCH v2 0/7] target-microblaze: Add support for BSXFI

[Qemu-devel] [PATCH v2 0/7] target-microblaze: Add support for BSXFI

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for bitfield extract and deposit instructions.
This is based on top of the Misc configurability series
I just sent out:
https://lists.nongnu.org/archive/html/qemu-devel/2017-06/msg04496.html

Cheers,
Edgar

ChangeLog:

v1 -> v2:
* Simplify undef behavior checks for BSIFI
* Add undef behavior checks for BSEFI

Edgar E. Iglesias (7):
  target-microblaze: dec_barrel: Use bool instead of unsigned int
  target-microblaze: dec_barrel: Use extract32
  target-microblaze: dec_barrel: Add braces around if-statements
  target-microblaze: dec_barrel: Plug TCG temp leak
  target-microblaze: dec_barrel: Add BSEFI
  target-microblaze: dec_barrel: Add BSIFI
  target-microblaze: Add CPU version 10.0

 target/microblaze/cpu.c       |  1 +
 target/microblaze/translate.c | 60 +++++++++++++++++++++++++++++++++----------
 2 files changed, 47 insertions(+), 14 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH v2 1/7] target-microblaze: dec_barrel: Use bool instead of unsigned int

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Use bool instead of unsigned int to represent flags.
No functional change.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index fbb8bb4..4136a8e 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -660,7 +660,7 @@ static void dec_div(DisasContext *dc)
 static void dec_barrel(DisasContext *dc)
 {
     TCGv t0;
-    unsigned int s, t;
+    bool s, t;
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-- 
2.7.4

[Qemu-devel] [PATCH v2 2/7] target-microblaze: dec_barrel: Use extract32

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Use extract32 instead of opencoding the shifting and masking.
No functional change.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 4136a8e..e959de7 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -670,8 +670,8 @@ static void dec_barrel(DisasContext *dc)
         return;
     }
 
-    s = dc->imm & (1 << 10);
-    t = dc->imm & (1 << 9);
+    s = extract32(dc->imm, 10, 1);
+    t = extract32(dc->imm, 9, 1);
 
     LOG_DIS("bs%s%s r%d r%d r%d\n",
             s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
-- 
2.7.4

[Qemu-devel] [PATCH v2 3/7] target-microblaze: dec_barrel: Add braces around if-statements

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add braces around if-statements.
No functional change.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index e959de7..504ed88 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -681,13 +681,14 @@ static void dec_barrel(DisasContext *dc)
     tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
     tcg_gen_andi_tl(t0, t0, 31);
 
-    if (s)
+    if (s) {
         tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
-    else {
-        if (t)
+    } else {
+        if (t) {
             tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
-        else
+        } else {
             tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+        }
     }
 }
 
-- 
2.7.4

[Qemu-devel] [PATCH v2 4/7] target-microblaze: dec_barrel: Plug TCG temp leak

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Plug TCG temp leak.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 504ed88..6ee4885 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -690,6 +690,7 @@ static void dec_barrel(DisasContext *dc)
             tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
         }
     }
+    tcg_temp_free(t0);
 }
 
 static void dec_bit(DisasContext *dc)
-- 
2.7.4

[Qemu-devel] [PATCH v2 5/7] target-microblaze: dec_barrel: Add BSEFI

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for BSEFI.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 42 ++++++++++++++++++++++++++++++------------
 1 file changed, 30 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6ee4885..3fad13c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -660,7 +660,8 @@ static void dec_div(DisasContext *dc)
 static void dec_barrel(DisasContext *dc)
 {
     TCGv t0;
-    bool s, t;
+    unsigned int imm_w, imm_s;
+    bool s, t, e = false;
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
@@ -670,27 +671,44 @@ static void dec_barrel(DisasContext *dc)
         return;
     }
 
+    if (dc->type_b) {
+        /* Insert and extract are only available in immediate mode.  */
+        e = extract32(dc->imm, 14, 1);
+    }
     s = extract32(dc->imm, 10, 1);
     t = extract32(dc->imm, 9, 1);
+    imm_w = extract32(dc->imm, 6, 5);
+    imm_s = extract32(dc->imm, 0, 5);
 
-    LOG_DIS("bs%s%s r%d r%d r%d\n",
+    LOG_DIS("bs%s%s%s r%d r%d r%d\n",
+            e ? "e" : "",
             s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
 
-    t0 = tcg_temp_new();
+    if (e) {
+        if (imm_w + imm_s > 32 || imm_w == 0) {
+            /* These inputs have an undefined behavior.  */
+            qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n",
+                          imm_w, imm_s);
+        } else {
+            tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
+        }
+    } else {
+        t0 = tcg_temp_new();
 
-    tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
-    tcg_gen_andi_tl(t0, t0, 31);
+        tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
+        tcg_gen_andi_tl(t0, t0, 31);
 
-    if (s) {
-        tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
-    } else {
-        if (t) {
-            tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+        if (s) {
+            tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
         } else {
-            tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+            if (t) {
+                tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+            } else {
+                tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+            }
         }
+        tcg_temp_free(t0);
     }
-    tcg_temp_free(t0);
 }
 
 static void dec_bit(DisasContext *dc)
-- 
2.7.4

[Qemu-devel] [PATCH v2 6/7] target-microblaze: dec_barrel: Add BSIFI

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for BSIFI.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 3fad13c..cb65d1e 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -661,7 +661,7 @@ static void dec_barrel(DisasContext *dc)
 {
     TCGv t0;
     unsigned int imm_w, imm_s;
-    bool s, t, e = false;
+    bool s, t, e = false, i = false;
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
@@ -673,6 +673,7 @@ static void dec_barrel(DisasContext *dc)
 
     if (dc->type_b) {
         /* Insert and extract are only available in immediate mode.  */
+        i = extract32(dc->imm, 15, 1);
         e = extract32(dc->imm, 14, 1);
     }
     s = extract32(dc->imm, 10, 1);
@@ -692,6 +693,17 @@ static void dec_barrel(DisasContext *dc)
         } else {
             tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
         }
+    } else if (i) {
+        int width = imm_w - imm_s + 1;
+
+        if (imm_w < imm_s) {
+            /* These inputs have an undefined behavior.  */
+            qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n",
+                          imm_w, imm_s);
+        } else {
+            tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra],
+                                imm_s, width);
+        }
     } else {
         t0 = tcg_temp_new();
 
-- 
2.7.4

[Qemu-devel] [PATCH v2 7/7] target-microblaze: Add CPU version 10.0

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add CPU version 10.0.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6e27c3c..f85ff01 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -67,6 +67,7 @@ static const struct {
     {"9.4", 0x21},
     {"9.5", 0x22},
     {"9.6", 0x23},
+    {"10.0", 0x24},
     {NULL, 0},
 };
 
-- 
2.7.4

Re: [Qemu-devel] [PATCH v2 6/7] target-microblaze: dec_barrel: Add BSIFI

[Richard Henderson]

On 06/21/2017 05:59 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"<edgar.iglesias@xilinx.com>
> 
> Add support for BSIFI.
> 
> Signed-off-by: Edgar E. Iglesias<edgar.iglesias@xilinx.com>
> ---
>   target/microblaze/translate.c | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~