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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <14a6a58c-6c0c-10de-888e-fcf528bf0728@linaro.org>
Date: Thu, 8 Feb 2018 06:40:22 -0800
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Subject: Re: [Qemu-devel] [PATCH v5 10/23] RISC-V Physical Memory Protection
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To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org>

On 02/07/2018 05:28 PM, Michael Clark wrote:
> Implements the physical memory protection extension as specified in
> Privileged ISA Version 1.10.
> 
> PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
> The SiFive verification team have PMP test cases that will be run.
> 
> Nothing currently depends on PMP support. It would be preferable to keep
> the code in-tree for folk that are interested in RISC-V PMP support.
> 
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  target/riscv/pmp.c | 386 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>  target/riscv/pmp.h |  70 ++++++++++
>  2 files changed, 456 insertions(+)
>  create mode 100644 target/riscv/pmp.c
>  create mode 100644 target/riscv/pmp.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~