From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYQyM-0002RM-9v for qemu-devel@nongnu.org; Fri, 21 Jul 2017 01:59:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dYQyJ-0001pf-3U for qemu-devel@nongnu.org; Fri, 21 Jul 2017 01:59:34 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:49387) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dYQyI-0001pI-SR for qemu-devel@nongnu.org; Fri, 21 Jul 2017 01:59:31 -0400 From: "Emilio G. Cota" Date: Fri, 21 Jul 2017 01:59:20 -0400 Message-Id: <1500616763-26560-3-git-send-email-cota@braap.org> In-Reply-To: <1500616763-26560-1-git-send-email-cota@braap.org> References: <1500616763-26560-1-git-send-email-cota@braap.org> Subject: [Qemu-devel] [PATCH v4 20/43] tcg: check CF_PARALLEL instead of parallel_cpus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Richard Henderson Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a field to TCGContext, storing there a copy of tb->cflags. Most architectures have <= 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the new field. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/tcg-op.c | 10 +++++----- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 96872f8..ef1760a 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,6 +656,7 @@ struct TCGContext { uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */ TCGRegSet reserved_regs; + uint32_t tb_cflags; /* cflags of the current TB */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c1ce38f..227b566 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1271,6 +1271,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags = flags; tb->cflags = cflags; tb->trace_vcpu_dstate = *cpu->trace_dstate; + tcg_ctx.tb_cflags = cflags; #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 205d07f..5580789 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,7 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2, void tcg_gen_mb(TCGBar mb_type) { - if (parallel_cpus) { + if (tcg_ctx.tb_cflags & CF_PARALLEL) { tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); } } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, { memop = tcg_canonicalize_memop(memop, 0, 0); - if (!parallel_cpus) { + if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t2 = tcg_temp_new_i32(); @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, { memop = tcg_canonicalize_memop(memop, 1, 0); - if (!parallel_cpus) { + if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] = { \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ -- 2.7.4