From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 1/7] target/arm: Correct MPU trace handling of write vs execute
Date: Mon, 31 Jul 2017 13:22:39 +0100 [thread overview]
Message-ID: <1501503765-15639-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org>
Correct off-by-one bug in the PSMAv7 MPU tracing where it would print
a write access as "reading", an insn fetch as "writing", and a read
access as "execute".
Since we have an MMUAccessType enum now, we can make the code clearer
in the process by using that rather than the raw 0/1/2 values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1500906792-18010-1-git-send-email-peter.maydell@linaro.org
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4ed32c5..9ed5096 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8558,8 +8558,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
phys_ptr, prot, fsr);
qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
- access_type == 1 ? "reading" :
- (access_type == 2 ? "writing" : "execute"),
+ access_type == MMU_DATA_LOAD ? "reading" :
+ (access_type == MMU_DATA_STORE ? "writing" : "execute"),
(uint32_t)address, mmu_idx,
ret ? "Miss" : "Hit",
*prot & PAGE_READ ? 'r' : '-',
--
2.7.4
next prev parent reply other threads:[~2017-07-31 12:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-31 12:22 [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell
2017-07-31 12:22 ` Peter Maydell [this message]
2017-07-31 12:22 ` [Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 3/7] target/arm: Don't allow guest to make System space executable for M profile Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 6/7] target/arm: Migrate MPU_RNR register state for M profile cores Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 7/7] hw/mps2_scc: fix incorrect properties Peter Maydell
2017-07-31 15:40 ` [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell
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