From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 6/7] target/arm: Migrate MPU_RNR register state for M profile cores
Date: Mon, 31 Jul 2017 13:22:44 +0100 [thread overview]
Message-ID: <1501503765-15639-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org>
The PMSAv7 region number register is migrated for R profile
cores using the cpreg scheme, but M profile doesn't use
cpregs, and so we weren't migrating the MPU_RNR register state
at all. Fix that by adding a migration subsection for the
M profile case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1501153150-19984-6-git-send-email-peter.maydell@linaro.org
---
target/arm/machine.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 93c1a78..1f66da4 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -171,6 +171,29 @@ static const VMStateDescription vmstate_pmsav7 = {
}
};
+static bool pmsav7_rnr_needed(void *opaque)
+{
+ ARMCPU *cpu = opaque;
+ CPUARMState *env = &cpu->env;
+
+ /* For R profile cores pmsav7.rnr is migrated via the cpreg
+ * "RGNR" definition in helper.h. For M profile we have to
+ * migrate it separately.
+ */
+ return arm_feature(env, ARM_FEATURE_M);
+}
+
+static const VMStateDescription vmstate_pmsav7_rnr = {
+ .name = "cpu/pmsav7-rnr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmsav7_rnr_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
VMStateField *field)
{
@@ -377,6 +400,11 @@ const VMStateDescription vmstate_arm_cpu = {
&vmstate_iwmmxt,
&vmstate_m,
&vmstate_thumb2ee,
+ /* pmsav7_rnr must come before pmsav7 so that we have the
+ * region number before we test it in the VMSTATE_VALIDATE
+ * in vmstate_pmsav7.
+ */
+ &vmstate_pmsav7_rnr,
&vmstate_pmsav7,
NULL
}
--
2.7.4
next prev parent reply other threads:[~2017-07-31 12:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-31 12:22 [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 1/7] target/arm: Correct MPU trace handling of write vs execute Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 3/7] target/arm: Don't allow guest to make System space executable for M profile Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset Peter Maydell
2017-07-31 12:22 ` Peter Maydell [this message]
2017-07-31 12:22 ` [Qemu-devel] [PULL 7/7] hw/mps2_scc: fix incorrect properties Peter Maydell
2017-07-31 15:40 ` [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell
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