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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 7/7] hw/mps2_scc: fix incorrect properties
Date: Mon, 31 Jul 2017 13:22:45 +0100	[thread overview]
Message-ID: <1501503765-15639-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170729234930.725-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/mps2-scc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index cc58d26..32be2a9 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -270,9 +270,9 @@ static Property mps2_scc_properties[] = {
     /* Values for various read-only ID registers (which are specific
      * to the board model or FPGA image)
      */
-    DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, aid, 0),
+    DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
     DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
-    DEFINE_PROP_UINT32("scc-id", MPS2SCC, aid, 0),
+    DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
     /* These are the initial settings for the source clocks on the board.
      * In hardware they can be configured via a config file read by the
      * motherboard configuration controller to suit the FPGA image.
-- 
2.7.4

  parent reply	other threads:[~2017-07-31 12:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-31 12:22 [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 1/7] target/arm: Correct MPU trace handling of write vs execute Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 3/7] target/arm: Don't allow guest to make System space executable for M profile Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset Peter Maydell
2017-07-31 12:22 ` [Qemu-devel] [PULL 6/7] target/arm: Migrate MPU_RNR register state for M profile cores Peter Maydell
2017-07-31 12:22 ` Peter Maydell [this message]
2017-07-31 15:40 ` [Qemu-devel] [PULL 0/7] target-arm queue Peter Maydell

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