From: Yongbok Kim <yongbok.kim@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
James Hogan <james.hogan@imgtec.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount
Date: Thu, 3 Aug 2017 15:45:15 +0100 [thread overview]
Message-ID: <1501771515-22847-9-git-send-email-yongbok.kim@imgtec.com> (raw)
In-Reply-To: <1501771515-22847-1-git-send-email-yongbok.kim@imgtec.com>
From: James Hogan <james.hogan@imgtec.com>
RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled
it must set can_do_io while it calls the helper to avoid the "Bad icount
read" error. It should also break out of the translation loop to ensure
that timer interrupts are immediately handled.
Fixes: 2e70f6efa8b9 ("Add instruction counter.")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
target/mips/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bcea2a1..c78d272 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -10755,8 +10755,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 2:
+ if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_rdhwr_cc(t0, cpu_env);
+ if (ctx->tb->cflags & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
gen_store_gpr(t0, rt);
+ /* Break the TB to be able to take timer interrupts immediately
+ after reading count. BS_STOP isn't sufficient, we need to ensure
+ we break completely out of translated code. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
break;
case 3:
gen_helper_rdhwr_ccres(t0, cpu_env);
--
2.7.4
next prev parent reply other threads:[~2017-08-03 14:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-03 14:45 [Qemu-devel] [PULL 0/8] target-mips queue Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScratch Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 2/8] mips/malta: leave space for the bootmap after the initrd Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 4/8] mips: Add KVM T&E segment support for TCG Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 5/8] target-mips: apply CP0.PageMask before writing into TLB entry Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 6/8] target/mips: Use BS_EXCP where interrupts are expected Yongbok Kim
2017-08-03 14:45 ` [Qemu-devel] [PULL 7/8] target/mips: Drop redundant gen_io_start/stop() Yongbok Kim
2017-08-03 14:45 ` Yongbok Kim [this message]
2017-08-04 12:46 ` [Qemu-devel] [PULL 0/8] target-mips queue Peter Maydell
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