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From: Aleksandr Bezzubikov <zuban32s@gmail.com>
To: qemu-devel@nongnu.org
Cc: mst@redhat.com, marcel@redhat.com, imammedo@redhat.com,
	pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com,
	kevin@koconnor.net, kraxel@redhat.com, lersek@redhat.com,
	seabios@seabios.org, Aleksandr Bezzubikov <zuban32s@gmail.com>
Subject: [Qemu-devel] [PATCH v4 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware
Date: Sat,  5 Aug 2017 23:27:36 +0300	[thread overview]
Message-ID: <1501964858-5159-4-git-send-email-zuban32s@gmail.com> (raw)
In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com>

On PCI init PCI bridges may need some extra info about bus number,
IO, memory and prefetchable memory to reserve. QEMU can provide this
with a special vendor-specific PCI capability.

Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
---
 hw/pci/pci_bridge.c         | 29 +++++++++++++++++++++++++++++
 include/hw/pci/pci_bridge.h | 21 +++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 720119b..889950d 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -408,6 +408,35 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
     br->bus_name = bus_name;
 }
 
+
+int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
+                              uint32_t bus_reserve, uint64_t io_reserve,
+                              uint64_t non_pref_mem_reserve,
+                              uint64_t pref_mem_reserve,
+                              Error **errp)
+{
+    size_t cap_len = sizeof(PCIBridgeQemuCap);
+    PCIBridgeQemuCap cap = {
+            .len = cap_len,
+            .type = REDHAT_PCI_CAP_QEMU_RESERVE,
+            .bus_res = bus_reserve,
+            .io = io_reserve,
+            .mem = non_pref_mem_reserve,
+            .mem_pref = pref_mem_reserve
+    };
+
+    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
+                                    cap_offset, cap_len, errp);
+    if (offset < 0) {
+        return offset;
+    }
+
+    memcpy(dev->config + offset + PCI_CAP_FLAGS,
+            (char *)&cap + PCI_CAP_FLAGS,
+            cap_len - PCI_CAP_FLAGS);
+    return 0;
+}
+
 static const TypeInfo pci_bridge_type_info = {
     .name = TYPE_PCI_BRIDGE,
     .parent = TYPE_PCI_DEVICE,
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index ff7cbaa..be565f7 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -67,4 +67,25 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 #define  PCI_BRIDGE_CTL_DISCARD_STATUS	0x400	/* Discard timer status */
 #define  PCI_BRIDGE_CTL_DISCARD_SERR	0x800	/* Discard timer SERR# enable */
 
+typedef struct PCIBridgeQemuCap {
+    uint8_t id;     /* Standard PCI capability header field */
+    uint8_t next;   /* Standard PCI capability header field */
+    uint8_t len;    /* Standard PCI vendor-specific capability header field */
+    uint8_t type;   /* Red Hat vendor-specific capability type.
+                       Types are defined with REDHAT_PCI_CAP_ prefix */
+
+    uint32_t bus_res;   /* Minimum number of buses to reserve */
+    uint64_t io;        /* IO space to reserve */
+    uint64_t mem;       /* Non-prefetchable memory to reserve */
+    uint64_t mem_pref;  /* Prefetchable memory to reserve */
+} PCIBridgeQemuCap;
+
+#define REDHAT_PCI_CAP_QEMU_RESERVE     1
+
+int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
+                              uint32_t bus_reserve, uint64_t io_reserve,
+                              uint64_t non_pref_mem_reserve,
+                              uint64_t pref_mem_reserve,
+                              Error **errp);
+
 #endif /* QEMU_PCI_BRIDGE_H */
-- 
2.7.4

  parent reply	other threads:[~2017-08-05 20:28 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-05 20:27 [Qemu-devel] [PATCH v4 0/5] Generic PCIE-PCI Bridge Aleksandr Bezzubikov
2017-08-05 20:27 ` [Qemu-devel] [PATCH v4 1/5] hw/i386: allow SHPC for Q35 machine Aleksandr Bezzubikov
2017-08-08 14:48   ` [Qemu-devel] acpi-test: Warning! DSDT mismatch (was: [PATCH v4 1/5] hw/i386: allow SHPC for Q35 machine) Thomas Huth
2017-08-08 15:35     ` Michael S. Tsirkin
2017-08-08 18:38       ` [Qemu-devel] acpi-test: Warning! DSDT mismatch Thomas Huth
2017-08-08 19:37         ` Michael S. Tsirkin
2017-08-05 20:27 ` [Qemu-devel] [PATCH v4 2/5] hw/pci: introduce pcie-pci-bridge device Aleksandr Bezzubikov
2017-08-07 16:39   ` Marcel Apfelbaum
2017-08-07 16:42     ` Alexander Bezzubikov
2017-08-07 16:54       ` Marcel Apfelbaum
2017-08-05 20:27 ` Aleksandr Bezzubikov [this message]
2017-08-07 16:44   ` [Qemu-devel] [PATCH v4 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware Marcel Apfelbaum
2017-08-05 20:27 ` [Qemu-devel] [PATCH v4 4/5] hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port Aleksandr Bezzubikov
2017-08-07 16:48   ` Marcel Apfelbaum
2017-08-08 19:54   ` Michael S. Tsirkin
2017-08-08 20:10     ` Aleksandr Bezzubikov
2017-08-08 20:15       ` Michael S. Tsirkin
2017-08-05 20:27 ` [Qemu-devel] [PATCH v4 5/5] docs: update documentation considering PCIE-PCI bridge Aleksandr Bezzubikov
2017-08-08 15:11   ` Laszlo Ersek
2017-08-08 19:21     ` Aleksandr Bezzubikov
2017-08-09 10:18       ` Laszlo Ersek
2017-08-09 16:52         ` Aleksandr Bezzubikov
2017-08-09 17:44           ` Laszlo Ersek

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