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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed() hook
Date: Mon,  4 Sep 2017 13:25:57 +0100	[thread overview]
Message-ID: <1504527967-29248-27-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1504527967-29248-1-git-send-email-peter.maydell@linaro.org>

Currently we have a rather half-baked setup for allowing CPUs to
generate exceptions on accesses to invalid memory: the CPU has a
cpu_unassigned_access() hook which the memory system calls in
unassigned_mem_write() and unassigned_mem_read() if the current_cpu
pointer is non-NULL.  This was originally designed before we
implemented the MemTxResult type that allows memory operations to
report a success or failure code, which is why the hook is called
right at the bottom of the memory system.  The major problem with
this is that it means that the hook can be called even when the
access was not actually done by the CPU: for instance if the CPU
writes to a DMA engine register which causes the DMA engine to begin
a transaction which has been set up by the guest to operate on
invalid memory then this will casue the CPU to take an exception
incorrectly.  Another minor problem is that currently if a device
returns a transaction error then this won't turn into a CPU exception
at all.

The right way to do this is to have allow the CPU to respond
to memory system transaction failures at the point where the
CPU specific code calls into the memory system.

Define a new QOM CPU method and utility function
cpu_transaction_failed() which is called in these cases.
The functionality here overlaps with the existing
cpu_unassigned_access() because individual target CPUs will
need some work to convert them to the new system. When this
transition is complete we can remove the old cpu_unassigned_access()
code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 include/qom/cpu.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index b7ac949..08bd868 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -85,8 +85,11 @@ struct TranslationBlock;
  * @has_work: Callback for checking if there is work to do.
  * @do_interrupt: Callback for interrupt handling.
  * @do_unassigned_access: Callback for unassigned access handling.
+ * (this is deprecated: new targets should use do_transaction_failed instead)
  * @do_unaligned_access: Callback for unaligned access handling, if
  * the target defines #ALIGNED_ONLY.
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  * runtime configurable endianness is currently big-endian. Non-configurable
  * CPUs can use the default implementation of this method. This method should
@@ -153,6 +156,10 @@ typedef struct CPUClass {
     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
                                 MMUAccessType access_type,
                                 int mmu_idx, uintptr_t retaddr);
+    void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+                                  unsigned size, MMUAccessType access_type,
+                                  int mmu_idx, MemTxAttrs attrs,
+                                  MemTxResult response, uintptr_t retaddr);
     bool (*virtio_is_big_endian)(CPUState *cpu);
     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
                            uint8_t *buf, int len, bool is_write);
@@ -847,6 +854,21 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 
     cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
 }
+
+static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
+                                          vaddr addr, unsigned size,
+                                          MMUAccessType access_type,
+                                          int mmu_idx, MemTxAttrs attrs,
+                                          MemTxResult response,
+                                          uintptr_t retaddr)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+
+    if (cc->do_transaction_failed) {
+        cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
+                                  mmu_idx, attrs, response, retaddr);
+    }
+}
 #endif
 
 #endif /* NEED_CPU_H */
-- 
2.7.4

  parent reply	other threads:[~2017-09-04 12:26 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-04 12:25 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 01/36] target/arm: Use MMUAccessType enum rather than int Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 02/36] target/arm: Don't trap WFI/WFE for M profile Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_phys_addr() Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where new v8M insns will be Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 05/36] hw/intc/armv7m_nvic.c: Remove out of date comment Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 06/36] target/arm: Remove incorrect comment about MPU_CTRL Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 07/36] target/arm: Fix outdated comment about exception exit Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode() Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 14/36] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 15/36] nvic: Implement "user accesses BusFault" SCS region behaviour Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 16/36] loader: Handle ELF files with overlapping zero-initialized data Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 17/36] loader: Ignore zero-sized ELF segments Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of hard-coded string Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 21/36] hw/arm/virt: allow pmu instantiation with userspace irqchip Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 22/36] target/arm/kvm: pmu: improve error handling Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the reset width register Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 24/36] aspeed_soc: Propagate silicon-rev to watchdog Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h Peter Maydell
2017-09-04 12:25 ` Peter Maydell [this message]
2017-09-04 12:25 ` [Qemu-devel] [PULL 27/36] cputlb: Support generating CPU exceptions on memory transaction failures Peter Maydell
2017-09-04 12:25 ` [Qemu-devel] [PULL 28/36] boards.h: Define new flag ignore_memory_transaction_failures Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 29/36] hw/arm: Set ignore_memory_transaction_failures for most ARM boards Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 30/36] target/arm: Factor out fault delivery code Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 31/36] target/arm: Allow deliver_fault() caller to specify EA bit Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 32/36] target/arm: Implement new do_transaction_failed hook Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 33/36] hw/arm/aspeed_soc: Mark devices as user_creatable = false Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 34/36] hw/arm/digic: Mark device with " Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback Peter Maydell
2017-09-04 12:26 ` [Qemu-devel] [PULL 36/36] arm_gicv3_kvm: Fix compile warning Peter Maydell

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