qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 26/31] target/arm: Move regime_is_secure() to target/arm/internals.h
Date: Thu,  7 Sep 2017 14:28:19 +0100	[thread overview]
Message-ID: <1504790904-17018-27-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org>

Move the regime_is_secure() utility function to internals.h;
we are going to want to call it from translate.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org
---
 target/arm/internals.h | 26 ++++++++++++++++++++++++++
 target/arm/helper.c    | 26 --------------------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 461f558..4afebd9 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -480,4 +480,30 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
     }
 }
 
+/* Return true if this address translation regime is secure */
+static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
+{
+    switch (mmu_idx) {
+    case ARMMMUIdx_S12NSE0:
+    case ARMMMUIdx_S12NSE1:
+    case ARMMMUIdx_S1NSE0:
+    case ARMMMUIdx_S1NSE1:
+    case ARMMMUIdx_S1E2:
+    case ARMMMUIdx_S2NS:
+    case ARMMMUIdx_MPriv:
+    case ARMMMUIdx_MNegPri:
+    case ARMMMUIdx_MUser:
+        return false;
+    case ARMMMUIdx_S1E3:
+    case ARMMMUIdx_S1SE0:
+    case ARMMMUIdx_S1SE1:
+    case ARMMMUIdx_MSPriv:
+    case ARMMMUIdx_MSNegPri:
+    case ARMMMUIdx_MSUser:
+        return true;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 #endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1c47f71..00807b4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7055,32 +7055,6 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
     }
 }
 
-/* Return true if this address translation regime is secure */
-static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
-    switch (mmu_idx) {
-    case ARMMMUIdx_S12NSE0:
-    case ARMMMUIdx_S12NSE1:
-    case ARMMMUIdx_S1NSE0:
-    case ARMMMUIdx_S1NSE1:
-    case ARMMMUIdx_S1E2:
-    case ARMMMUIdx_S2NS:
-    case ARMMMUIdx_MPriv:
-    case ARMMMUIdx_MNegPri:
-    case ARMMMUIdx_MUser:
-        return false;
-    case ARMMMUIdx_S1E3:
-    case ARMMMUIdx_S1SE0:
-    case ARMMMUIdx_S1SE1:
-    case ARMMMUIdx_MSPriv:
-    case ARMMMUIdx_MSNegPri:
-    case ARMMMUIdx_MSUser:
-        return true;
-    default:
-        g_assert_not_reached();
-    }
-}
-
 /* Return the SCTLR value which controls this address translation regime */
 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
-- 
2.7.4

  parent reply	other threads:[~2017-09-07 13:28 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-07 13:27 [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 01/31] armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 03/31] gicv3: Convert " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 04/31] xlnx_zynqmp: " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 05/31] xilinx_axienet: " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 06/31] xilinx_axidma: " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 07/31] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 09/31] target/arm: Implement new PMSAv8 behaviour Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 12/31] target/arm: Add MMU indexes for secure v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 13/31] target/arm: Make BASEPRI register banked for v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 15/31] target/arm: Make FAULTMASK " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 16/31] target/arm: Make CONTROL " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 20/31] target/arm: Make MPU_RBAR, MPU_RLAR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 23/31] target/arm: Make CCR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 24/31] target/arm: Make MMFAR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 25/31] target/arm: Make CFSR register " Peter Maydell
2017-09-07 13:28 ` Peter Maydell [this message]
2017-09-07 13:28 ` [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature Peter Maydell
2017-09-07 16:48 ` [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1504790904-17018-27-git-send-email-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).