From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK
Date: Thu, 7 Sep 2017 14:27:56 +0100 [thread overview]
Message-ID: <1504790904-17018-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org>
From: Fam Zheng <famz@redhat.com>
Signed-off-by: Fam Zheng <famz@redhat.com>
Message-id: 20170905131149.10669-4-famz@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_its_kvm.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 1f8991b..39903d5 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -120,17 +120,6 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
qemu_add_vm_change_state_handler(vm_change_state_handler, s);
}
-static void kvm_arm_its_init(Object *obj)
-{
- GICv3ITSState *s = KVM_ARM_ITS(obj);
-
- object_property_add_link(obj, "parent-gicv3",
- "kvm-arm-gicv3", (Object **)&s->gicv3,
- object_property_allow_set_link,
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
- &error_abort);
-}
-
/**
* kvm_arm_its_pre_save - handles the saving of ITS registers.
* ITS tables are flushed into guest RAM separately and earlier,
@@ -205,12 +194,19 @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
GITS_CTLR, &s->ctlr, true, &error_abort);
}
+static Property kvm_arm_its_props[] = {
+ DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
+ GICv3State *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
dc->realize = kvm_arm_its_realize;
+ dc->props = kvm_arm_its_props;
icc->send_msi = kvm_its_send_msi;
icc->pre_save = kvm_arm_its_pre_save;
icc->post_load = kvm_arm_its_post_load;
@@ -220,7 +216,6 @@ static const TypeInfo kvm_arm_its_info = {
.name = TYPE_KVM_ARM_ITS,
.parent = TYPE_ARM_GICV3_ITS_COMMON,
.instance_size = sizeof(GICv3ITSState),
- .instance_init = kvm_arm_its_init,
.class_init = kvm_arm_its_class_init,
};
--
2.7.4
next prev parent reply other threads:[~2017-09-07 13:28 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-07 13:27 [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 01/31] armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory " Peter Maydell
2017-09-07 13:27 ` Peter Maydell [this message]
2017-09-07 13:27 ` [Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 05/31] xilinx_axienet: " Peter Maydell
2017-09-07 13:27 ` [Qemu-devel] [PULL 06/31] xilinx_axidma: " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 07/31] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 09/31] target/arm: Implement new PMSAv8 behaviour Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 12/31] target/arm: Add MMU indexes for secure v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 13/31] target/arm: Make BASEPRI register banked for v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 15/31] target/arm: Make FAULTMASK " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 16/31] target/arm: Make CONTROL " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 20/31] target/arm: Make MPU_RBAR, MPU_RLAR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 23/31] target/arm: Make CCR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 24/31] target/arm: Make MMFAR " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 25/31] target/arm: Make CFSR register " Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 26/31] target/arm: Move regime_is_secure() to target/arm/internals.h Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook Peter Maydell
2017-09-07 13:28 ` [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature Peter Maydell
2017-09-07 16:48 ` [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell
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