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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/18] xlnx-zcu102: Manually create the machines
Date: Thu, 14 Sep 2017 18:52:44 +0100	[thread overview]
Message-ID: <1505411573-27848-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org>

From: Alistair Francis <alistair.francis@xilinx.com>

In preperation for future work let's manually create the Xilnx machines.
This will allow us to set properties for the machines in the future.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 67 insertions(+), 7 deletions(-)

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index e9702ed..5b1f184 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -26,15 +26,24 @@
 #include "qemu/log.h"
 
 typedef struct XlnxZCU102 {
+    MachineState parent_obj;
+
     XlnxZynqMPState soc;
     MemoryRegion ddr_ram;
 } XlnxZCU102;
 
+#define TYPE_ZCU102_MACHINE   MACHINE_TYPE_NAME("xlnx-zcu102")
+#define ZCU102_MACHINE(obj) \
+    OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
+
+#define TYPE_EP108_MACHINE   MACHINE_TYPE_NAME("xlnx-ep108")
+#define EP108_MACHINE(obj) \
+    OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE)
+
 static struct arm_boot_info xlnx_zcu102_binfo;
 
-static void xlnx_zcu102_init(MachineState *machine)
+static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
 {
-    XlnxZCU102 *s = g_new0(XlnxZCU102, 1);
     int i;
     uint64_t ram_size = machine->ram_size;
 
@@ -116,19 +125,56 @@ static void xlnx_zcu102_init(MachineState *machine)
     arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
 }
 
-static void xlnx_ep108_machine_init(MachineClass *mc)
+static void xlnx_ep108_init(MachineState *machine)
+{
+    XlnxZCU102 *s = EP108_MACHINE(machine);
+
+    xlnx_zynqmp_init(s, machine);
+}
+
+static void xlnx_ep108_machine_instance_init(Object *obj)
 {
+}
+
+static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
     mc->desc = "Xilinx ZynqMP EP108 board";
-    mc->init = xlnx_zcu102_init;
+    mc->init = xlnx_ep108_init;
     mc->block_default_type = IF_IDE;
     mc->units_per_default_bus = 1;
     mc->ignore_memory_transaction_failures = true;
 }
 
-DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
+static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("xlnx-ep108"),
+    .parent     = TYPE_MACHINE,
+    .class_init = xlnx_ep108_machine_class_init,
+    .instance_init = xlnx_ep108_machine_instance_init,
+    .instance_size = sizeof(XlnxZCU102),
+};
 
-static void xlnx_zcu102_machine_init(MachineClass *mc)
+static void xlnx_ep108_machine_init_register_types(void)
 {
+    type_register_static(&xlnx_ep108_machine_init_typeinfo);
+}
+
+static void xlnx_zcu102_init(MachineState *machine)
+{
+    XlnxZCU102 *s = ZCU102_MACHINE(machine);
+
+    xlnx_zynqmp_init(s, machine);
+}
+
+static void xlnx_zcu102_machine_instance_init(Object *obj)
+{
+}
+
+static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
     mc->desc = "Xilinx ZynqMP ZCU102 board";
     mc->init = xlnx_zcu102_init;
     mc->block_default_type = IF_IDE;
@@ -136,4 +182,18 @@ static void xlnx_zcu102_machine_init(MachineClass *mc)
     mc->ignore_memory_transaction_failures = true;
 }
 
-DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init)
+static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("xlnx-zcu102"),
+    .parent     = TYPE_MACHINE,
+    .class_init = xlnx_zcu102_machine_class_init,
+    .instance_init = xlnx_zcu102_machine_instance_init,
+    .instance_size = sizeof(XlnxZCU102),
+};
+
+static void xlnx_zcu102_machine_init_register_types(void)
+{
+    type_register_static(&xlnx_zcu102_machine_init_typeinfo);
+}
+
+type_init(xlnx_zcu102_machine_init_register_types)
+type_init(xlnx_ep108_machine_init_register_types)
-- 
2.7.4

  parent reply	other threads:[~2017-09-14 17:52 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-14 17:52 [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102 Peter Maydell
2017-09-14 17:52 ` Peter Maydell [this message]
2017-09-14 17:52 ` [Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 18/18] mps2-an511: Fix wiring of UART overflow interrupt lines Peter Maydell
2017-09-15 17:59 ` [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell

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