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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction
Date: Thu, 14 Sep 2017 18:52:48 +0100	[thread overview]
Message-ID: <1505411573-27848-14-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org>

From: Jaroslaw Pelczar <j.pelczar@samsung.com>

Previously when single stepping through ERET instruction via GDB
would result in debugger entering the "next" PC after ERET instruction.
When debugging in kernel mode, this will also cause unintended behavior,
because debugger will try to access memory from EL0 point of view.

Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com>
Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9017e30..1bc12d9 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11348,6 +11348,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         default:
             gen_a64_set_pc_im(dc->pc);
             /* fall through */
+        case DISAS_EXIT:
         case DISAS_JUMP:
             if (dc->base.singlestep_enabled) {
                 gen_exception_internal(EXCP_DEBUG);
-- 
2.7.4

  parent reply	other threads:[~2017-09-14 17:52 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-14 17:52 [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102 Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 09/18] xlnx-zcu102: Manually create the machines Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated Peter Maydell
2017-09-14 17:52 ` Peter Maydell [this message]
2017-09-14 17:52 ` [Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing Peter Maydell
2017-09-14 17:52 ` [Qemu-devel] [PULL 18/18] mps2-an511: Fix wiring of UART overflow interrupt lines Peter Maydell
2017-09-15 17:59 ` [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell

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