From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 24/31] hw/timer/omap_gptimer: Don't use old_mmio
Date: Thu, 21 Sep 2017 17:41:32 +0100 [thread overview]
Message-ID: <1506012099-13605-25-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1506012099-13605-1-git-send-email-peter.maydell@linaro.org>
Don't use the old_mmio struct in memory region ops.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
---
hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
1 file changed, 37 insertions(+), 12 deletions(-)
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
index 5e3e8a6..6d7c8a3 100644
--- a/hw/timer/omap_gptimer.c
+++ b/hw/timer/omap_gptimer.c
@@ -450,19 +450,44 @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
s->writeh = (uint16_t) value;
}
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ switch (size) {
+ case 1:
+ return omap_badwidth_read32(opaque, addr);
+ case 2:
+ return omap_gp_timer_readh(opaque, addr);
+ case 4:
+ return omap_gp_timer_readw(opaque, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ switch (size) {
+ case 1:
+ omap_badwidth_write32(opaque, addr, value);
+ break;
+ case 2:
+ omap_gp_timer_writeh(opaque, addr, value);
+ break;
+ case 4:
+ omap_gp_timer_write(opaque, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static const MemoryRegionOps omap_gp_timer_ops = {
- .old_mmio = {
- .read = {
- omap_badwidth_read32,
- omap_gp_timer_readh,
- omap_gp_timer_readw,
- },
- .write = {
- omap_badwidth_write32,
- omap_gp_timer_writeh,
- omap_gp_timer_write,
- },
- },
+ .read = omap_gp_timer_readfn,
+ .write = omap_gp_timer_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};
--
2.7.4
next prev parent reply other threads:[~2017-09-21 16:41 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-21 16:41 [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 02/31] nvic: Add banked exception states Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 03/31] nvic: Add cached vectpending_is_s_banked state Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 07/31] nvic: Implement NVIC_ITNS<n> registers Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state() Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1 Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio() Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index() Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 18/31] nvic: Make SHCSR " Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 19/31] nvic: Support banked exceptions in acknowledge and complete Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 20/31] target/arm: Remove out of date ARM ARM section references in A64 decoder Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 22/31] hw/gpio/omap_gpio.c: Don't use old_mmio Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 23/31] hw/timer/omap_synctimer.c: " Peter Maydell
2017-09-21 16:41 ` Peter Maydell [this message]
2017-09-21 16:41 ` [Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: " Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 26/31] hw/arm/omap2.c: " Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 27/31] msf2: Add Smartfusion2 System timer Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 28/31] msf2: Microsemi Smartfusion2 System Register block Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 29/31] msf2: Add Smartfusion2 SPI controller Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 30/31] msf2: Add Smartfusion2 SoC Peter Maydell
2017-09-21 16:41 ` [Qemu-devel] [PULL 31/31] msf2: Add Emcraft's Smartfusion2 SOM kit Peter Maydell
2017-09-21 17:28 ` [Qemu-devel] [PULL 00/31] target-arm queue Peter Maydell
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