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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M
Date: Fri, 22 Sep 2017 15:59:57 +0100	[thread overview]
Message-ID: <1506092407-26985-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1506092407-26985-1-git-send-email-peter.maydell@linaro.org>

In v8M, more bits are defined in the exception-return magic
values; update the code that checks these so we accept
the v8M values when the CPU permits them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 58 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 59a07d2..da3a36e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6275,8 +6275,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
     uint32_t excret;
     uint32_t xpsr;
     bool ufault = false;
-    bool return_to_sp_process = false;
-    bool return_to_handler = false;
+    bool sfault = false;
+    bool return_to_sp_process;
+    bool return_to_handler;
     bool rettobase = false;
     bool exc_secure = false;
     bool return_to_secure;
@@ -6310,6 +6311,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
                       excret);
     }
 
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+        /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
+         * we pick which FAULTMASK to clear.
+         */
+        if (!env->v7m.secure &&
+            ((excret & R_V7M_EXCRET_ES_MASK) ||
+             !(excret & R_V7M_EXCRET_DCRS_MASK))) {
+            sfault = 1;
+            /* For all other purposes, treat ES as 0 (R_HXSR) */
+            excret &= ~R_V7M_EXCRET_ES_MASK;
+        }
+    }
+
     if (env->v7m.exception != ARMV7M_EXCP_NMI) {
         /* Auto-clear FAULTMASK on return from other than NMI.
          * If the security extension is implemented then this only
@@ -6347,24 +6361,53 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
         g_assert_not_reached();
     }
 
+    return_to_handler = !(excret & R_V7M_EXCRET_MODE_MASK);
+    return_to_sp_process = excret & R_V7M_EXCRET_SPSEL_MASK;
     return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
         (excret & R_V7M_EXCRET_S_MASK);
 
-    switch (excret & 0xf) {
-    case 1: /* Return to Handler */
-        return_to_handler = true;
-        break;
-    case 13: /* Return to Thread using Process stack */
-        return_to_sp_process = true;
-        /* fall through */
-    case 9: /* Return to Thread using Main stack */
-        if (!rettobase &&
-            !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) {
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+            /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
+             * we choose to take the UsageFault.
+             */
+            if ((excret & R_V7M_EXCRET_S_MASK) ||
+                (excret & R_V7M_EXCRET_ES_MASK) ||
+                !(excret & R_V7M_EXCRET_DCRS_MASK)) {
+                ufault = true;
+            }
+        }
+        if (excret & R_V7M_EXCRET_RES0_MASK) {
             ufault = true;
         }
-        break;
-    default:
-        ufault = true;
+    } else {
+        /* For v7M we only recognize certain combinations of the low bits */
+        switch (excret & 0xf) {
+        case 1: /* Return to Handler */
+            break;
+        case 13: /* Return to Thread using Process stack */
+        case 9: /* Return to Thread using Main stack */
+            /* We only need to check NONBASETHRDENA for v7M, because in
+             * v8M this bit does not exist (it is RES1).
+             */
+            if (!rettobase &&
+                !(env->v7m.ccr[env->v7m.secure] &
+                  R_V7M_CCR_NONBASETHRDENA_MASK)) {
+                ufault = true;
+            }
+            break;
+        default:
+            ufault = true;
+        }
+    }
+
+    if (sfault) {
+        env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+        v7m_exception_taken(cpu, excret);
+        qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing "
+                      "stackframe: failed EXC_RETURN.ES validity check\n");
+        return;
     }
 
     if (ufault) {
-- 
2.7.4

  parent reply	other threads:[~2017-09-22 14:59 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 14:59 [Qemu-devel] [PATCH 00/20] ARM v8M: exception entry, exit and security Peter Maydell
2017-09-22 14:59 ` [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-09-23  0:34   ` Richard Henderson
2017-09-29 21:03   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-22 14:59 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-05  4:44   ` Philippe Mathieu-Daudé
2017-10-05 16:04   ` Richard Henderson
2017-10-05 16:20     ` Peter Maydell
2017-10-06 13:22       ` Peter Maydell
2017-10-06 13:24         ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-10-05  3:25   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:09   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-05 16:14   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-10-05 16:18   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-10-05 16:25   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-09-29 21:05   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:28   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-09-29 21:07   ` Philippe Mathieu-Daudé
2017-10-05 16:32   ` Richard Henderson
2017-10-05 16:34     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-10-05 16:39   ` Richard Henderson
2017-09-22 14:59 ` Peter Maydell [this message]
2017-10-05 17:16   ` [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context Peter Maydell
2017-10-05 17:30   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 12/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-10-05 18:31   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-10-05 18:33   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-10-05 18:39   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-10-05  4:46   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:41   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-10-05  3:29   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:42   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction Peter Maydell
2017-09-22 17:18   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2017-10-05 18:50   ` [Qemu-devel] " Richard Henderson
2017-10-05 18:55     ` Peter Maydell
2017-10-05 18:57       ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS Peter Maydell
2017-10-05 13:07   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:56   ` [Qemu-devel] " Richard Henderson
2017-10-05 19:40     ` Peter Maydell
2017-09-22 15:00 ` [Qemu-devel] [PATCH 19/20] target/arm: Implement secure function return Peter Maydell
2017-10-05 13:11   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:00   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-10-05  4:33   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:01   ` [Qemu-devel] " Richard Henderson
2017-10-05  4:51 ` [Qemu-devel] [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Philippe Mathieu-Daudé
2017-10-06 13:29 ` Peter Maydell

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