From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy7Dh-0002Yo-NX for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dy7Dg-0005IE-OV for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:33 -0400 From: Aaron Lindsay Date: Fri, 29 Sep 2017 22:08:26 -0400 Message-Id: <1506737310-21880-10-git-send-email-alindsay@codeaurora.org> In-Reply-To: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> References: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> Subject: [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Peter Crosthwaite , Wei Huang Cc: qemu-devel@nongnu.org, Michael Spradling , Aaron Lindsay , Digant Desai List-ID: This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 10 ++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dfadaad..da14864 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -830,6 +830,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &= ~0xf00; + } else { + uint64_t pmceid = get_pmceid(&cpu->env); + cpu->pmceid0 = pmceid & 0xffffffff; + cpu->pmceid1 = (pmceid >> 32) & 0xffffffff; } if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 365a809..9feb45a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -835,6 +835,16 @@ void pmccntr_sync(CPUARMState *env); */ void pmu_sync(CPUARMState *env); +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters which + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/helper.c b/target/arm/helper.c index c0ef367..a56e7b4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -891,6 +891,43 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) - 1)) +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01]) */ + bool (*supported)(CPUARMState *); + /* Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +#define SUPPORTED_EVENT_SENTINEL UINT16_MAX +static const pm_event pm_events[] = { + { .number = SUPPORTED_EVENT_SENTINEL } +}; +static uint16_t supported_event_map[0x3f]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid = 0; + unsigned int i = 0; + while (pm_events[i].number != SUPPORTED_EVENT_SENTINEL) { + const pm_event *cnt = &pm_events[i]; + if (cnt->number < 0x3f && cnt->supported(env)) { + pmceid |= (1 << cnt->number); + supported_event_map[cnt->number] = i; + } else { + supported_event_map[cnt->number] = SUPPORTED_EVENT_SENTINEL; + } + i++; + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a Linux Foundation Collaborative Project.