From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy7Dm-0002f9-PC for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dy7Dl-0005Mu-Ns for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:38 -0400 From: Aaron Lindsay Date: Fri, 29 Sep 2017 22:08:29 -0400 Message-Id: <1506737310-21880-13-git-send-email-alindsay@codeaurora.org> In-Reply-To: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> References: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> Subject: [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Peter Crosthwaite , Wei Huang Cc: qemu-devel@nongnu.org, Michael Spradling , Aaron Lindsay , Digant Desai List-ID: This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e48bb67..659b2b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4926,7 +4926,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL0_RW, .accessfn = pmreg_access, .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue = cpu->midr & 0xff000000, + /* 4 counters enabled */ + .resetvalue = (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT), .writefn = pmcr_write, .raw_writefn = raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a Linux Foundation Collaborative Project.