From: Aaron Lindsay <alindsay@codeaurora.org>
To: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
Wei Huang <wei@redhat.com>
Cc: qemu-devel@nongnu.org,
Michael Spradling <mspradli@codeaurora.org>,
Aaron Lindsay <alindsay@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>
Subject: [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled
Date: Fri, 29 Sep 2017 22:08:19 -0400 [thread overview]
Message-ID: <1506737310-21880-3-git-send-email-alindsay@codeaurora.org> (raw)
In-Reply-To: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org>
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8be78ea..40c9273 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -964,7 +964,7 @@ static inline bool arm_ccnt_enabled(CPUARMState *env)
{
/* This does not support checking PMCCFILTR_EL0 register */
- if (!(env->cp15.c9_pmcr & PMCRE)) {
+ if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) {
return false;
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2017-09-30 2:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-30 2:08 [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0] Aaron Lindsay
2017-09-30 2:08 ` Aaron Lindsay [this message]
2017-10-17 12:49 ` [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Peter Maydell
2017-10-17 14:59 ` Aaron Lindsay
2017-10-17 15:00 ` Peter Maydell
2017-09-30 2:08 ` [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync Aaron Lindsay
2017-10-17 13:25 ` Peter Maydell
2017-10-17 15:26 ` Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N Aaron Lindsay
2017-10-17 13:41 ` Peter Maydell
2017-10-17 15:42 ` Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2017-10-17 13:52 ` Peter Maydell
2017-09-30 2:08 ` [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2017-10-17 14:57 ` Peter Maydell
2017-10-17 19:32 ` Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET Aaron Lindsay
2017-10-17 14:19 ` Peter Maydell
2017-10-17 16:02 ` Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled Aaron Lindsay
2017-10-17 14:04 ` Peter Maydell
2017-09-30 2:08 ` [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC Aaron Lindsay
2017-10-09 14:46 ` [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2017-10-09 18:27 ` Peter Maydell
2017-10-09 20:25 ` Aaron Lindsay
2017-10-17 15:09 ` Peter Maydell
2017-10-17 19:52 ` Aaron Lindsay
-- strict thread matches above, loose matches on Subject: below --
2017-04-19 17:41 [Qemu-devel] [PATCH " Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Aaron Lindsay
2017-10-17 12:48 ` Peter Maydell
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