From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy7Dd-0002Tf-Oz for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dy7Dc-0005CM-Rl for qemu-devel@nongnu.org; Fri, 29 Sep 2017 22:09:29 -0400 From: Aaron Lindsay Date: Fri, 29 Sep 2017 22:08:22 -0400 Message-Id: <1506737310-21880-6-git-send-email-alindsay@codeaurora.org> In-Reply-To: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> References: <1506737310-21880-1-git-send-email-alindsay@codeaurora.org> Subject: [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Peter Crosthwaite , Wei Huang Cc: qemu-devel@nongnu.org, Michael Spradling , Aaron Lindsay , Digant Desai List-ID: Also fix the existing bitmask for writes. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 54070a3..fcc2fcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1059,10 +1059,25 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { pmccntr_sync(env); - env->cp15.pmccfiltr_el0 = value & 0x7E000000; + env->cp15.pmccfiltr_el0 = value & 0xfc000000; pmccntr_sync(env); } +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_sync(env); + env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & 0x04000000) | + (value & 0xf8000000); /* M is not visible in AArch32 */ + pmccntr_sync(env); +} + +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & 0xf8000000; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1280,6 +1295,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .type = ARM_CP_IO, .readfn = pmccntr_read, .writefn = pmccntr_write, }, #endif + { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, + .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetoflow32(CPUARMState, cp15.pmccfiltr_el0), + .resetvalue = 0, }, { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, .writefn = pmccfiltr_write, -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a Linux Foundation Collaborative Project.