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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 14/20] target/arm: Add support for restoring v8M additional state context
Date: Fri,  6 Oct 2017 16:59:39 +0100	[thread overview]
Message-ID: <1507305585-20608-15-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1507305585-20608-1-git-send-email-peter.maydell@linaro.org>

For v8M, exceptions from Secure to Non-Secure state will save
callee-saved registers to the exception frame as well as the
caller-saved registers. Add support for unstacking these
registers in exception exit when necessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-12-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4aa32d0..f93a214 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6463,6 +6463,36 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
                           "for destination state is UNPREDICTABLE\n");
         }
 
+        /* Do we need to pop callee-saved registers? */
+        if (return_to_secure &&
+            ((excret & R_V7M_EXCRET_ES_MASK) == 0 ||
+             (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) {
+            uint32_t expected_sig = 0xfefa125b;
+            uint32_t actual_sig = ldl_phys(cs->as, frameptr);
+
+            if (expected_sig != actual_sig) {
+                /* Take a SecureFault on the current stack */
+                env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK;
+                armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+                v7m_exception_taken(cpu, excret);
+                qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing "
+                              "stackframe: failed exception return integrity "
+                              "signature check\n");
+                return;
+            }
+
+            env->regs[4] = ldl_phys(cs->as, frameptr + 0x8);
+            env->regs[5] = ldl_phys(cs->as, frameptr + 0xc);
+            env->regs[6] = ldl_phys(cs->as, frameptr + 0x10);
+            env->regs[7] = ldl_phys(cs->as, frameptr + 0x14);
+            env->regs[8] = ldl_phys(cs->as, frameptr + 0x18);
+            env->regs[9] = ldl_phys(cs->as, frameptr + 0x1c);
+            env->regs[10] = ldl_phys(cs->as, frameptr + 0x20);
+            env->regs[11] = ldl_phys(cs->as, frameptr + 0x24);
+
+            frameptr += 0x28;
+        }
+
         /* Pop registers. TODO: make these accesses use the correct
          * attributes and address space (S/NS, priv/unpriv) and handle
          * memory transaction failures.
-- 
2.7.4

  parent reply	other threads:[~2017-10-06 15:59 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-06 15:59 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 01/20] arm: Fix SMC reporting to EL2 when QEMU provides PSCI Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 02/20] hw/sd: fix out-of-bounds check for multi block reads Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 03/20] hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 05/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 06/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 08/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 09/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 10/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 12/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 13/20] target/arm: Update excret sanity checks for v8M Peter Maydell
2017-10-06 15:59 ` Peter Maydell [this message]
2017-10-06 15:59 ` [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 16/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 17/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-10-06 15:59 ` [Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-10-06 16:44 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell

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