From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e6Go6-0005Ht-6x for qemu-devel@nongnu.org; Sun, 22 Oct 2017 10:00:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e6Go3-0002b1-5d for qemu-devel@nongnu.org; Sun, 22 Oct 2017 10:00:50 -0400 From: Subbaraya Sundeep Date: Sun, 22 Oct 2017 18:58:02 +0530 Message-Id: <1508678882-4327-1-git-send-email-sundeep.lkml@gmail.com> Subject: [Qemu-devel] [Qemu devel v3 PATCH] msf2: Remove dead code reported by Coverity List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, alistair23@gmail.com, f4bug@amsat.org, imammedo@redhat.com, pbonzini@redhat.com, darren.kenny@oracle.com, Subbaraya Sundeep Fixed incorrect frame size mask, validated maximum frame size in spi_write and removed dead code. Signed-off-by: Subbaraya Sundeep --- v3: Added comment that [31:6] bits are reserved in R_SPI_DFSIZE register and logged incorrect value too in guest error(suggested by Darren). v2: else if -> else in set_fifodepth log guest error when frame size is more than 32 hw/ssi/mss-spi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c index 5a8e308..e1b6227 100644 --- a/hw/ssi/mss-spi.c +++ b/hw/ssi/mss-spi.c @@ -76,9 +76,10 @@ #define C_BIGFIFO (1 << 29) #define C_RESET (1 << 31) -#define FRAMESZ_MASK 0x1F +#define FRAMESZ_MASK 0x3F #define FMCOUNT_MASK 0x00FFFF00 #define FMCOUNT_SHIFT 8 +#define FRAMESZ_MAX 32 static void txfifo_reset(MSSSpiState *s) { @@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s) s->fifo_depth = 32; } else if (size <= 16) { s->fifo_depth = 16; - } else if (size <= 32) { - s->fifo_depth = 8; } else { - s->fifo_depth = 4; + s->fifo_depth = 8; } } @@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr, if (s->enabled) { break; } + /* + * [31:6] bits are reserved bits and for future use. + * [5:0] are for frame size. Only [5:0] bits are validated + * during write, [31:6] bits are untouched. + */ + if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %d provided." + "Maximum frame size is %d\n", + __func__, value & FRAMESZ_MASK, FRAMESZ_MAX); + break; + } s->regs[R_SPI_DFSIZE] = value; break; -- 2.5.0