From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Richard Henderson" <rth@twiddle.net>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [PATCH 5/7] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()
Date: Fri, 1 Dec 2017 18:44:37 +0000 [thread overview]
Message-ID: <1512153879-5291-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1512153879-5291-1-git-send-email-peter.maydell@linaro.org>
The TT instruction is going to need to look up the MMU index
for a specified security and privilege state. Refactor the
existing arm_v7m_mmu_idx_for_secstate() into a version that
lets you specify the privilege state and one that uses the
current state of the CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d228fe6..1f414fd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2334,14 +2334,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
-/* Return the MMU index for a v7M CPU in the specified security state */
-static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
- bool secstate)
+/* Return the MMU index for a v7M CPU in the specified security and
+ * privilege state
+ */
+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate,
+ bool priv)
{
- int el = arm_current_el(env);
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
- if (el != 0) {
+ if (priv) {
mmu_idx |= 1;
}
@@ -2356,6 +2358,15 @@ static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
return mmu_idx;
}
+/* Return the MMU index for a v7M CPU in the specified security state */
+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
+ bool secstate)
+{
+ bool priv = arm_current_el(env) != 0;
+
+ return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
/* Determine the current mmu_idx to use for normal loads/stores */
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
--
2.7.4
next prev parent reply other threads:[~2017-12-01 18:44 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-01 18:44 [Qemu-devel] [PATCH 0/7] armv8m: Implement TT, and other bugfixes Peter Maydell
2017-12-01 18:44 ` [Qemu-devel] [PATCH 1/7] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads Peter Maydell
2017-12-03 14:58 ` Richard Henderson
2017-12-05 18:54 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 2/7] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode Peter Maydell
2017-12-03 15:03 ` Richard Henderson
2017-12-01 18:44 ` [Qemu-devel] [PATCH 3/7] target/arm: Add missing M profile case to regime_is_user() Peter Maydell
2017-12-03 15:04 ` Richard Henderson
2017-12-05 18:58 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 4/7] target/arm: Split M profile MNegPri mmu index into user and priv Peter Maydell
2017-12-03 15:09 ` Richard Henderson
2017-12-05 21:23 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-07 11:07 ` Peter Maydell
2017-12-07 14:15 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` Peter Maydell [this message]
2017-12-03 15:12 ` [Qemu-devel] [PATCH 5/7] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() Richard Henderson
2017-12-05 21:24 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 6/7] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() Peter Maydell
2017-12-03 15:16 ` Richard Henderson
2017-12-05 21:27 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 7/7] target/arm: Implement TT instruction Peter Maydell
2017-12-03 16:04 ` Richard Henderson
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