From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 22/43] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()
Date: Wed, 13 Dec 2017 18:12:20 +0000 [thread overview]
Message-ID: <1513188761-20784-23-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org>
The TT instruction is going to need to look up the MMU index
for a specified security and privilege state. Refactor the
existing arm_v7m_mmu_idx_for_secstate() into a version that
lets you specify the privilege state and one that uses the
current state of the CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1512153879-5291-6-git-send-email-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.h | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c42d62d..9631670 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2339,14 +2339,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
-/* Return the MMU index for a v7M CPU in the specified security state */
-static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
- bool secstate)
+/* Return the MMU index for a v7M CPU in the specified security and
+ * privilege state
+ */
+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate,
+ bool priv)
{
- int el = arm_current_el(env);
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
- if (el != 0) {
+ if (priv) {
mmu_idx |= ARM_MMU_IDX_M_PRIV;
}
@@ -2361,6 +2363,15 @@ static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
return mmu_idx;
}
+/* Return the MMU index for a v7M CPU in the specified security state */
+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
+ bool secstate)
+{
+ bool priv = arm_current_el(env) != 0;
+
+ return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
/* Determine the current mmu_idx to use for normal loads/stores */
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
--
2.7.4
next prev parent reply other threads:[~2017-12-13 18:13 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-13 18:11 [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell
2017-12-13 18:11 ` [Qemu-devel] [PULL 01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13 Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 13/43] xlnx-zcu102: Add support for the ZynqMP QSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 16/43] linux-headers: update to 4.15-rc1 Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 21/43] target/arm: Split M profile MNegPri mmu index into user and priv Peter Maydell
2017-12-13 18:12 ` Peter Maydell [this message]
2017-12-13 18:12 ` [Qemu-devel] [PULL 23/43] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 24/43] target/arm: Implement TT instruction Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 25/43] target/arm: Provide fault type enum and FSR conversion functions Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 26/43] target/arm: Remove fsr argument from arm_ld*_ptw() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 27/43] target/arm: Convert get_phys_addr_v5() to not return FSC values Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 28/43] target/arm: Convert get_phys_addr_v6() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 29/43] target/arm: Convert get_phys_addr_lpae() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 31/43] target/arm: Convert get_phys_addr_pmsav7() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 32/43] target/arm: Convert get_phys_addr_pmsav8() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 33/43] target/arm: Use ARMMMUFaultInfo in deliver_fault() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 34/43] target/arm: Ignore fsr from get_phys_addr() in do_ats_write() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 36/43] target/arm: Extend PAR format determination Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 37/43] nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 38/43] nvic: Make systick banked Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 39/43] hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 40/43] MAINTAINERS: replace the unavailable email address Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 41/43] xilinx_spips: Update the QSPI Mod ID reset value Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 42/43] xilinx_spips: Set all of the reset values Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 43/43] xilinx_spips: Use memset instead of a for loop to zero registers Peter Maydell
2017-12-14 15:32 ` [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell
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