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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 37/43] nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion
Date: Wed, 13 Dec 2017 18:12:35 +0000	[thread overview]
Message-ID: <1513188761-20784-38-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1513188761-20784-1-git-send-email-peter.maydell@linaro.org>

Generalize nvic_sysreg_ns_ops so that we can pass it an
arbitrary MemoryRegion which it will use as the underlying
register implementation to apply the NS-alias behaviour
to. We'll want this so we can do the same with systick.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1512154296-5652-2-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 5d9c883..63f2743 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1786,10 +1786,12 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
                                         uint64_t value, unsigned size,
                                         MemTxAttrs attrs)
 {
+    MemoryRegion *mr = opaque;
+
     if (attrs.secure) {
         /* S accesses to the alias act like NS accesses to the real region */
         attrs.secure = 0;
-        return nvic_sysreg_write(opaque, addr, value, size, attrs);
+        return memory_region_dispatch_write(mr, addr, value, size, attrs);
     } else {
         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
         if (attrs.user) {
@@ -1803,10 +1805,12 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
                                        uint64_t *data, unsigned size,
                                        MemTxAttrs attrs)
 {
+    MemoryRegion *mr = opaque;
+
     if (attrs.secure) {
         /* S accesses to the alias act like NS accesses to the real region */
         attrs.secure = 0;
-        return nvic_sysreg_read(opaque, addr, data, size, attrs);
+        return memory_region_dispatch_read(mr, addr, data, size, attrs);
     } else {
         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
         if (attrs.user) {
@@ -2075,7 +2079,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
 
     if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
         memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
-                              &nvic_sysreg_ns_ops, s,
+                              &nvic_sysreg_ns_ops, &s->sysregmem,
                               "nvic_sysregs_ns", 0x1000);
         memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
     }
-- 
2.7.4

  parent reply	other threads:[~2017-12-13 18:13 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-13 18:11 [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell
2017-12-13 18:11 ` [Qemu-devel] [PULL 01/43] m25p80: Add support for continuous read out of RDSR and READ_FSR Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13 Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 05/43] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 06/43] xilinx_spips: Update striping to be big-endian bit order Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 13/43] xlnx-zcu102: Add support for the ZynqMP QSPI Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 16/43] linux-headers: update to 4.15-rc1 Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 19/43] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 21/43] target/arm: Split M profile MNegPri mmu index into user and priv Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 22/43] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 23/43] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 24/43] target/arm: Implement TT instruction Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 25/43] target/arm: Provide fault type enum and FSR conversion functions Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 26/43] target/arm: Remove fsr argument from arm_ld*_ptw() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 27/43] target/arm: Convert get_phys_addr_v5() to not return FSC values Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 28/43] target/arm: Convert get_phys_addr_v6() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 29/43] target/arm: Convert get_phys_addr_lpae() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 31/43] target/arm: Convert get_phys_addr_pmsav7() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 32/43] target/arm: Convert get_phys_addr_pmsav8() " Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 33/43] target/arm: Use ARMMMUFaultInfo in deliver_fault() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 34/43] target/arm: Ignore fsr from get_phys_addr() in do_ats_write() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 35/43] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill() Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 36/43] target/arm: Extend PAR format determination Peter Maydell
2017-12-13 18:12 ` Peter Maydell [this message]
2017-12-13 18:12 ` [Qemu-devel] [PULL 38/43] nvic: Make systick banked Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 39/43] hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 40/43] MAINTAINERS: replace the unavailable email address Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 41/43] xilinx_spips: Update the QSPI Mod ID reset value Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 42/43] xilinx_spips: Set all of the reset values Peter Maydell
2017-12-13 18:12 ` [Qemu-devel] [PULL 43/43] xilinx_spips: Use memset instead of a for loop to zero registers Peter Maydell
2017-12-14 15:32 ` [Qemu-devel] [PULL 00/43] target-arm queue Peter Maydell

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