From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches+subscribe@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition
Date: Wed, 10 Jan 2018 15:46:21 -0800 [thread overview]
Message-ID: <1515628000-93285-3-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1515628000-93285-1-git-send-email-mjc@sifive.com>
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword;
#define EM_UNICORE32 110 /* UniCore32 */
+#define EM_RISCV 243 /* RISC-V */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.
--
2.7.0
next prev parent reply other threads:[~2018-01-10 23:48 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-10 23:46 [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers Michael Clark
2018-01-10 23:46 ` Michael Clark [this message]
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-15 13:44 ` Igor Mammedov
2018-01-24 18:21 ` Michael Clark
2018-01-29 15:37 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 8:08 ` Christoph Hellwig
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array Michael Clark
2018-01-15 13:19 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines Michael Clark
2018-01-15 13:27 ` Igor Mammedov
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 " Michael Clark
2018-01-10 23:46 ` [Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-11 0:05 ` [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2 Michael Clark
2018-01-11 0:46 ` no-reply
2018-01-11 7:58 ` Christoph Hellwig
2018-01-11 18:24 ` Michael Clark
2018-01-12 8:09 ` Christoph Hellwig
2018-01-12 19:50 ` Palmer Dabbelt
2018-01-11 19:16 ` Palmer Dabbelt
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