From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure
Date: Wed, 10 Jan 2018 18:22:04 -0800 [thread overview]
Message-ID: <1515637324-96034-22-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1515637324-96034-1-git-send-email-mjc@sifive.com>
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.
Expected checkpatch errors for consistency reasons:
ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Signed-off-by: Michael Clark <mjc@sifive.com>
---
Makefile.objs | 1 +
arch_init.c | 2 ++
configure | 11 +++++++++++
cpus.c | 6 ++++++
default-configs/riscv32-linux-user.mak | 1 +
default-configs/riscv32-softmmu.mak | 4 ++++
default-configs/riscv64-linux-user.mak | 1 +
default-configs/riscv64-softmmu.mak | 4 ++++
hw/riscv/Makefile.objs | 12 ++++++++++++
include/sysemu/arch_init.h | 1 +
qapi-schema.json | 14 +++++++++++++-
scripts/qemu-binfmt-conf.sh | 13 ++++++++++++-
target/riscv/Makefile.objs | 2 ++
target/riscv/trace-events | 1 +
14 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 default-configs/riscv32-linux-user.mak
create mode 100644 default-configs/riscv32-softmmu.mak
create mode 100644 default-configs/riscv64-linux-user.mak
create mode 100644 default-configs/riscv64-softmmu.mak
create mode 100644 hw/riscv/Makefile.objs
create mode 100644 target/riscv/Makefile.objs
create mode 100644 target/riscv/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 285c6f3..ae8658e 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -164,6 +164,7 @@ trace-events-subdirs += target/mips
trace-events-subdirs += target/sparc
trace-events-subdirs += target/s390x
trace-events-subdirs += target/ppc
+trace-events-subdirs += target/riscv
trace-events-subdirs += qom
trace-events-subdirs += linux-user
trace-events-subdirs += qapi
diff --git a/arch_init.c b/arch_init.c
index a0b8ed6..dcf356b 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -69,6 +69,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_OPENRISC
#elif defined(TARGET_PPC)
#define QEMU_ARCH QEMU_ARCH_PPC
+#elif defined(TARGET_RISCV)
+#define QEMU_ARCH QEMU_ARCH_RISCV
#elif defined(TARGET_S390X)
#define QEMU_ARCH QEMU_ARCH_S390X
#elif defined(TARGET_SH4)
diff --git a/configure b/configure
index 6a04082..a8151f9 100755
--- a/configure
+++ b/configure
@@ -6565,6 +6565,14 @@ case "$target_name" in
echo "TARGET_ABI32=y" >> $config_target_mak
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
+ riscv32)
+ TARGET_BASE_ARCH=riscv
+ TARGET_ABI_DIR=riscv
+ ;;
+ riscv64)
+ TARGET_BASE_ARCH=riscv
+ TARGET_ABI_DIR=riscv
+ ;;
sh4|sh4eb)
TARGET_ARCH=sh4
bflt="yes"
@@ -6730,6 +6738,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
ppc*)
disas_config "PPC"
;;
+ riscv)
+ disas_config "RISCV"
+ ;;
s390*)
disas_config "S390"
;;
diff --git a/cpus.c b/cpus.c
index e8139de..499be10 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1995,6 +1995,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_SPARC)
SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
CPUSPARCState *env = &sparc_cpu->env;
+#elif defined(TARGET_RISCV)
+ RISCVCPU *riscv_cpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &riscv_cpu->env;
#elif defined(TARGET_MIPS)
MIPSCPU *mips_cpu = MIPS_CPU(cpu);
CPUMIPSState *env = &mips_cpu->env;
@@ -2028,6 +2031,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_TRICORE)
info->value->arch = CPU_INFO_ARCH_TRICORE;
info->value->u.tricore.PC = env->PC;
+#elif defined(TARGET_RISCV)
+ info->value->arch = CPU_INFO_ARCH_RISCV;
+ info->value->u.riscv.pc = env->pc;
#else
info->value->arch = CPU_INFO_ARCH_OTHER;
#endif
diff --git a/default-configs/riscv32-linux-user.mak b/default-configs/riscv32-linux-user.mak
new file mode 100644
index 0000000..865b362
--- /dev/null
+++ b/default-configs/riscv32-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for riscv-linux-user
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
new file mode 100644
index 0000000..f9e7421
--- /dev/null
+++ b/default-configs/riscv32-softmmu.mak
@@ -0,0 +1,4 @@
+# Default configuration for riscv-softmmu
+
+CONFIG_SERIAL=y
+CONFIG_VIRTIO=y
diff --git a/default-configs/riscv64-linux-user.mak b/default-configs/riscv64-linux-user.mak
new file mode 100644
index 0000000..865b362
--- /dev/null
+++ b/default-configs/riscv64-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for riscv-linux-user
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
new file mode 100644
index 0000000..f9e7421
--- /dev/null
+++ b/default-configs/riscv64-softmmu.mak
@@ -0,0 +1,4 @@
+# Default configuration for riscv-softmmu
+
+CONFIG_SERIAL=y
+CONFIG_VIRTIO=y
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
new file mode 100644
index 0000000..a0c31ae
--- /dev/null
+++ b/hw/riscv/Makefile.objs
@@ -0,0 +1,12 @@
+obj-y += riscv_elf.o
+obj-y += riscv_htif.o
+obj-y += riscv_hart.o
+obj-y += sifive_e300.o
+obj-y += sifive_clint.o
+obj-y += sifive_prci.o
+obj-y += sifive_plic.o
+obj-y += sifive_u500.o
+obj-y += sifive_uart.o
+obj-y += spike_v1_09.o
+obj-y += spike_v1_10.o
+obj-y += virt.o
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 8751c46..63c6152 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
QEMU_ARCH_MOXIE = (1 << 15),
QEMU_ARCH_TRICORE = (1 << 16),
QEMU_ARCH_NIOS2 = (1 << 17),
+ QEMU_ARCH_RISCV = (1 << 18),
};
extern const uint32_t arch_type;
diff --git a/qapi-schema.json b/qapi-schema.json
index 5c06745..42d91f3 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -413,7 +413,7 @@
# Since: 2.6
##
{ 'enum': 'CpuInfoArch',
- 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
+ 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }
##
# @CpuInfo:
@@ -452,6 +452,7 @@
'ppc': 'CpuInfoPPC',
'mips': 'CpuInfoMIPS',
'tricore': 'CpuInfoTricore',
+ 'riscv': 'CpuInfoRISCV',
'other': 'CpuInfoOther' } }
##
@@ -512,6 +513,17 @@
{ 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } }
##
+# @CpuInfoRISCV:
+#
+# Additional information about a virtual RISCV CPU
+#
+# @pc: the instruction pointer
+#
+# Since 2.12
+##
+{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
+
+##
# @CpuInfoOther:
#
# No additional information is available about the virtual CPU
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 8afc3eb..c5ac660 100755
--- a/scripts/qemu-binfmt-conf.sh
+++ b/scripts/qemu-binfmt-conf.sh
@@ -4,7 +4,7 @@
qemu_target_list="i386 i486 alpha arm sparc32plus ppc ppc64 ppc64le m68k \
mips mipsel mipsn32 mipsn32el mips64 mips64el \
-sh4 sh4eb s390x aarch64 hppa"
+sh4 sh4eb s390x aarch64 hppa riscv32 riscv64"
i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00'
i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
@@ -96,6 +96,14 @@ hppa_magic='\x7f\x45\x4c\x46\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
hppa_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
hppa_family=hppa
+riscv32_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'
+riscv32_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
+riscv32_family=riscv
+
+riscv64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'
+riscv64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
+riscv64_family=riscv
+
qemu_get_family() {
cpu=${HOST_ARCH:-$(uname -m)}
case "$cpu" in
@@ -117,6 +125,9 @@ qemu_get_family() {
sparc*)
echo "sparc"
;;
+ riscv*)
+ echo "riscv"
+ ;;
*)
echo "$cpu"
;;
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
new file mode 100644
index 0000000..b9e9877
--- /dev/null
+++ b/target/riscv/Makefile.objs
@@ -0,0 +1,2 @@
+obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o \
+ user_atomic.o gdbstub.o pmp.o
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
new file mode 100644
index 0000000..9284b1f
--- /dev/null
+++ b/target/riscv/trace-events
@@ -0,0 +1 @@
+# See docs/devel/tracing.txt for syntax documentation.
--
2.7.0
next prev parent reply other threads:[~2018-01-11 2:23 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-11 2:21 [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-11 14:32 ` Richard Henderson
2018-01-11 14:37 ` Richard Henderson
2018-01-11 17:55 ` Michael Clark
2018-01-12 3:03 ` Palmer Dabbelt
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler Michael Clark
2018-01-11 14:34 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 15:29 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support Michael Clark
2018-01-11 15:31 ` Richard Henderson
2018-01-11 18:09 ` Michael Clark
2018-01-11 20:01 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub Michael Clark
2018-01-11 15:31 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-11 15:47 ` Richard Henderson
2018-01-11 18:15 ` Michael Clark
2018-01-11 18:55 ` Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-11 9:10 ` Antony Pavlov
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-12 10:13 ` Antony Pavlov
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 " Michael Clark
2018-01-11 2:22 ` Michael Clark [this message]
2018-01-11 14:05 ` [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure Eric Blake
2018-01-11 18:43 ` Michael Clark
2018-02-04 21:15 ` Michael Clark
2018-01-11 3:01 ` [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 no-reply
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