From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
RISC-V Patches <patches@groups.riscv.org>
Subject: [Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub
Date: Wed, 10 Jan 2018 18:21:50 -0800 [thread overview]
Message-ID: <1515637324-96034-8-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1515637324-96034-1-git-send-email-mjc@sifive.com>
GDB Register read and write routines.
Signed-off-by: Michael Clark <mjc@sifive.com>
---
target/riscv/gdbstub.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new file mode 100644
index 0000000..12d1d9f
--- /dev/null
+++ b/target/riscv/gdbstub.c
@@ -0,0 +1,59 @@
+/*
+ * RISC-V GDB Server Stub
+ *
+ * Author: Sagar Karandikar, sagark@eecs.berkeley.edu
+ *
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+#include "cpu.h"
+
+int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ /* TODO proper x0 handling */
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (n < 32) {
+ return gdb_get_regl(mem_buf, env->gpr[n]);
+ } else if (n == 32) {
+ return gdb_get_regl(mem_buf, env->pc);
+ } else if (n < 65) {
+ return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
+ }
+ return 0;
+}
+
+int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ /* TODO proper x0 handling */
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (n < 32) {
+ env->gpr[n] = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n == 32) {
+ env->pc = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n < 65) {
+ env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
+ return sizeof(uint64_t);
+ }
+ return 0;
+}
--
2.7.0
next prev parent reply other threads:[~2018-01-11 2:23 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-11 2:21 [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition Michael Clark
2018-01-11 14:32 ` Richard Henderson
2018-01-11 14:37 ` Richard Henderson
2018-01-11 17:55 ` Michael Clark
2018-01-12 3:03 ` Palmer Dabbelt
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler Michael Clark
2018-01-11 14:34 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers Michael Clark
2018-01-11 15:29 ` Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support Michael Clark
2018-01-11 15:31 ` Richard Henderson
2018-01-11 18:09 ` Michael Clark
2018-01-11 20:01 ` Richard Henderson
2018-01-11 2:21 ` Michael Clark [this message]
2018-01-11 15:31 ` [Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub Richard Henderson
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation Michael Clark
2018-01-11 15:47 ` Richard Henderson
2018-01-11 18:15 ` Michael Clark
2018-01-11 18:55 ` Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block Michael Clark
2018-01-11 9:10 ` Antony Pavlov
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines Michael Clark
2018-01-11 2:21 ` [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-01-12 10:13 ` Antony Pavlov
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 " Michael Clark
2018-01-11 2:22 ` [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure Michael Clark
2018-01-11 14:05 ` Eric Blake
2018-01-11 18:43 ` Michael Clark
2018-02-04 21:15 ` Michael Clark
2018-01-11 3:01 ` [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 no-reply
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