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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 24/26] target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions
Date: Thu, 11 Jan 2018 13:38:20 +0000	[thread overview]
Message-ID: <1515677902-23436-25-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1515677902-23436-1-git-send-email-peter.maydell@linaro.org>

Refactor disas_thumb2_insn() so that it generates the code for raising
an UNDEF exception for invalid insns, rather than returning a flag
which the caller must check to see if it needs to generate the UNDEF
code. This brings the function in to line with the behaviour of
disas_thumb_insn() and disas_arm_insn().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1513080506-17703-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index c690658..781be1e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9775,9 +9775,8 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
     return 0;
 }
 
-/* Translate a 32-bit thumb instruction.  Returns nonzero if the instruction
-   is not legal.  */
-static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
+/* Translate a 32-bit thumb instruction. */
+static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
 {
     uint32_t imm, shift, offset;
     uint32_t rd, rn, rm, rs;
@@ -11016,16 +11015,16 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
                     /* UNPREDICTABLE, unallocated hint or
                      * PLD/PLDW/PLI (literal)
                      */
-                    return 0;
+                    return;
                 }
                 if (op1 & 1) {
-                    return 0; /* PLD/PLDW/PLI or unallocated hint */
+                    return; /* PLD/PLDW/PLI or unallocated hint */
                 }
                 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
-                    return 0; /* PLD/PLDW/PLI or unallocated hint */
+                    return; /* PLD/PLDW/PLI or unallocated hint */
                 }
                 /* UNDEF space, or an UNPREDICTABLE */
-                return 1;
+                goto illegal_op;
             }
         }
         memidx = get_mem_index(s);
@@ -11151,9 +11150,10 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
     default:
         goto illegal_op;
     }
-    return 0;
+    return;
 illegal_op:
-    return 1;
+    gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+                       default_exception_el(s));
 }
 
 static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@@ -12275,10 +12275,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     if (is_16bit) {
         disas_thumb_insn(dc, insn);
     } else {
-        if (disas_thumb2_insn(dc, insn)) {
-            gen_exception_insn(dc, 4, EXCP_UDEF, syn_uncategorized(),
-                               default_exception_el(dc));
-        }
+        disas_thumb2_insn(dc, insn);
     }
 
     /* Advance the Thumb condexec condition.  */
-- 
2.7.4

  parent reply	other threads:[~2018-01-11 13:38 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-11 13:37 [Qemu-devel] [PULL 00/26] target-arm queue Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 01/26] linux-user: Add support for big-endian aarch64 Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 02/26] linux-user: Add separate aarch64_be uname Peter Maydell
2018-01-11 13:37 ` [Qemu-devel] [PULL 03/26] linux-user: Fix endianess of aarch64 signal trampoline Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 04/26] configure: Add aarch64_be-linux-user target Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 05/26] linux-user: Add aarch64_be magic numbers to qemu-binfmt-conf.sh Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 06/26] linux-user: Separate binfmt arm CPU families Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 07/26] linux-user: Activate armeb handler registration Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 08/26] target/arm: Fix stlxp for aarch64_be Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 09/26] Virt: ACPI: fix qemu assert due to re-assigned table data address Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 10/26] imx_fec: Do not link to netdev Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 11/26] imx_fec: Refactor imx_eth_enable_rx() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 12/26] imx_fec: Change queue flushing heuristics Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 13/26] imx_fec: Move Tx frame buffer away from the stack Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 14/26] imx_fec: Use ENET_FTRL to determine truncation length Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 15/26] imx_fec: Use MIN instead of explicit ternary operator Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 16/26] imx_fec: Emulate SHIFT16 in ENETx_RACC Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 17/26] imx_fec: Add support for multiple Tx DMA rings Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 18/26] imx_fec: Use correct length for packet size Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 19/26] imx_fec: Fix a typo in imx_enet_receive() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 20/26] imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 21/26] hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask() Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 22/26] hw/sd/pxa2xx_mmci: add read/write() trace events Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 23/26] linux-user/arm/nwfpe: Check coprocessor number for FPA emulation Peter Maydell
2018-01-11 13:38 ` Peter Maydell [this message]
2018-01-11 13:38 ` [Qemu-devel] [PULL 25/26] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI Peter Maydell
2018-01-11 13:38 ` [Qemu-devel] [PULL 26/26] hw/intc/arm_gic: reserved register addresses are RAZ/WI Peter Maydell
2018-01-11 14:19 ` [Qemu-devel] [PULL 00/26] target-arm queue no-reply
2018-01-11 15:24 ` Peter Maydell

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